---
title: "AWS builds its net by buying: who are Trn3's pick-and-shovel suppliers?"
type: "Topics"
locale: "en"
url: "https://longbridge.com/en/dolphin/post/44296262.md"
description: "Among cloud players developing in-house AI chips, AWS is the outlier. It designs its own silicon. For networking, it buys rather than builds whenever it can."
datetime: "2026-10-13T03:09:42.000Z"
locales:
  - [en](https://longbridge.com/en/dolphin/post/44296262.md)
  - [zh-CN](https://longbridge.com/zh-CN/dolphin/post/44296262.md)
  - [zh-HK](https://longbridge.com/zh-HK/dolphin/post/44296262.md)
author: "[Dolphin Research](https://longbridge.com/en/dolphin.md)"
generator: "portal-rs"
---

# AWS builds its net by buying: who are Trn3's pick-and-shovel suppliers?

In the prior piece (see [link](https://longbridge.com/en/dolphin/post/44283715?channel=OWNN00110)), we broke down AWS’s two-step 'shortcut' for AWS: the Scale-Up protocol NeuronLink essentially wraps PCIe for faster time-to-delivery. Trn2’s all-copper, 'stitched' 3D torus tops out at 64 cards, prompting AWS to pivot from Google’s direct-connect approach to NVIDIA’s switch-based design.

So how does the flagship Trn3 'buy' a switch-based fabric using off-the-shelf parts, and where does it differ from GB300? Where does AWS’s money in the stack actually go? We continue the teardown below.

The main text follows:

**I. Trn3: a switch-based fabric 'bought' off the shelf**

**1) A rack form factor similar to GB300**

Take the flagship Trn3 NL72x2 as an example. The design largely mirrors NVIDIA’s NVL72 switch-based architecture with 72 accelerators per rack and a sandwich-style tray layout (compute tray – switch tray – compute tray).

![IMG_268](https://pub.pbkrs.com/cms/2026/0/GKXoumBaB1NASfQfJF5ooMcRykkMovrP.jpg?x-oss-process=style/lg)

It is called Trn3 NL72x2 because two 72-accelerator racks ship as a single deliverable SKU, i.e., a 144-accelerator Scale-Up domain. The racks are linked using active electrical cables (AECs).

AECs are used for cross-rack links because passive copper is distance-limited, while optics are pricey and less reliable. For short runs between adjacent racks, AECs are a pragmatic choice, with chips at identical relative positions in the two racks directly paired via AECs as shown below.

![IMG_269](https://pub.pbkrs.com/cms/2026/0/EtiqHudbyG2BuXySgd7ZKGgR3RekqWiz.jpg?x-oss-process=style/lg)

![IMG_270](https://pub.pbkrs.com/cms/2026/0/J1TPuVAUVq3DF566LHBvvG8XV1KmwcMj.jpg?x-oss-process=style/lg)

**A natural question is: why 144 accelerators?** The core reason is to offset Trn3’s weaker compute and bandwidth. As shown, a single Trn3’s FP8 throughput is about half of GB300’s. Two racks, or 144 Trn3s, roughly match one GB300 NVL72 rack on FP8 compute and HBM capacity.

![IMG_271](https://pub.pbkrs.com/cms/2026/0/jwbXy4T5x6W1h5epbGKH6ckR1dPPqW2M.jpg?x-oss-process=style/lg)

**With the high-level design and system-level parity laid out, the more important question is how to understand Trn3’s fabric and its differences.**

**2) How to think about Trn3’s fabric vs. peers?**

We have emphasized that Trn3 uses a switch-based fabric, which can be interpreted with NVIDIA’s model in mind. GB300’s Scale-Up (intra-tray and inter-tray) is a 72-accelerator full mesh, forwarded by NV Switch ASICs on an in-rack switch tray.

Traffic within the domain takes a single hop, yielding ultra-low latency. Please refer to our earlier deep dives for details.

![IMG_272](https://pub.pbkrs.com/cms/2026/0/nbHXkBXLuLotitL4yAyK14wS7krUbYM9.jpg?x-oss-process=style/lg)

![IMG_273](https://pub.pbkrs.com/cms/2026/0/4Pg5hKwez8WA1FvAFKNJWW75hWVAV8Cf.jpg?x-oss-process=style/lg)

In AWS Trn3, intra-domain connections also require switch ASIC forwarding. However, the fabric is not yet fully connected and needs multiple hops, so end-to-end latency lags.

**3) How is a non-fully connected switch fabric implemented?**

The compute tray components are shown below, with the red box highlighting Scale-Up elements discussed previously. The most critical difference is that each Trn3 compute tray integrates eight Scorpio-P switch ASICs (labeled PCIe Switch below).

By contrast, GB300 has no on-tray switch ASICs, as all switches sit on the separate switch tray. Trn3 NL72x2 still uses a switch tray, built on Scorpio-X switch ASICs, and we explain below why both types are needed. Note: both Scorpio-P and Scorpio-X come from Astera Labs.

![IMG_274](https://pub.pbkrs.com/cms/2026/0/1m8ToP7Y21EK8YPg163qReg4oMCFK1N6.jpg?x-oss-process=style/lg)

From a dataflow view, GB300’s full-mesh Scale-Up path simplifies to: source GPU → backplane copper → NVSwitch ASIC → backplane copper → destination GPU. Full mesh is possible because a single NVSwitch has 72 ports to connect all 72 GPUs in the domain.

In Trn3, a Scorpio-X on the switch tray exposes only 18 usable ports, mapping to 18 compute trays. Each switch ASIC on the tray can only connect to one Trn3 per compute tray.

But a single compute tray has four Trn3s, which forces four independent 'vertical ladders' (as shown). Nodes on the same ladder can interconnect in one hop, but with four chips per tray, you end up with four ladders, and Scorpio-X lacks ports to directly link ladders.

![IMG_275](https://pub.pbkrs.com/cms/2026/0/NdVQoKJiuGtPiPegiZx1DmkAGWtvSA7d.jpg?x-oss-process=style/lg)

To interconnect ladders, traffic must drop down to the eight on-tray Scorpio-P chips mentioned earlier. The reason for eight is that within a ladder across trays, each compute chip connects to 10 switch chips, with each switch providing eight lanes, totaling 80 lanes per compute chip.

Each on-tray switch has only 32 lanes shared by four chips on the tray, so each chip gets eight. Deploying eight P-switches supplies 64 lanes, keeping intra-tray paths to one hop and aligning cross-tray, same-ladder paths to similar lane rates.

![IMG_276](https://pub.pbkrs.com/cms/2026/0/ym9PgaXNj3oquHEXoFYQPSXXQVj7uMJz.jpg?x-oss-process=style/lg)

In short, a Trn3 NL72x2 domain is built with cross-rack AEC links. Within a rack, the switch-based fabric resembles GB300, but due to limited switch-tray ports, the topology is multi-plane.

As a result, switches exist on both the compute tray and switch tray, and full connectivity is not yet achieved.

**4) Cross-rack: extra hops and cross-rack penalties**

We previously noted Google’s efforts to reduce hop counts to curb latency in v8i (for inference). What about hop counts (and latency) inside a Trn3 NL72x2 domain?

Consider chip A1 on rack A, tray 1, reaching C9 across rack B: to A9 (same plane) it’s one hop via Scorpio-X. To C9, it detours via Scorpio-P to switch planes, taking three hops.

Reaching C9′ on rack B adds a cross-rack relay, totaling four hops, as illustrated.

![IMG_277](https://pub.pbkrs.com/cms/2026/0/FKHjwk1Y3FAYaEqJ3KpEeP1VxVgJ5c8P.jpg?x-oss-process=style/lg)

**5) How to fix it? Wait for more ports on standard parts**

The multi-hop, multi-plane setup stems from too few switch ports. AWS plans three iterations within Trn3’s lifecycle by replacing only the switch-tray ASIC (Scorpio-X).

With the third iteration adopting UALink, the rack becomes one hop. Until then, hops remain higher.

**a) Gen 1, 160-lane Scorpio-X PCIe 6.0:** four planes per rack, up to three hops within a rack and four across racks.

**b) Gen 2, 320-lane Scorpio-X PCIe 6.0:** ports double, planes drop from four to two, and adjacent chips on a tray still interconnect via Scorpio-P.

**c) Gen 3, 72+ port UALink switch:** each switch connects to every Trn3 in the rack, enabling full mesh and one-hop in-rack paths. Cross-rack still needs two hops, lowering end-to-end latency overall.

On-tray switch ASICs are no longer mandatory transit points but remain a cost item.

![IMG_278](https://pub.pbkrs.com/cms/2026/0/v2YHwCFPBm5xMewMzcAnCAHEFXK69hn6.jpg?x-oss-process=style/lg)

**II. Summary: fast to ship, but can it go the distance?**

Together with the prior piece, AWS’s strategy does not rely on in-house differentiation or peak performance. It picks immediately available standard parts to build a low-cost fabric.

In other words, it is optimized for speed to deploy rather than bespoke engineering. That is the overarching theme.

**Scale-Up:**

\- At the protocol layer, NeuronLink on PCIe is a convenience choice and will likely be replaced over time. That is the expected trajectory.

\- On topology, the large-scale 3D torus demands heavy software and infra lift, pushing AWS toward a switch-based network. That shift was more necessity than choice.

Yet switch ASICs are standard parts with limited ports. Even on a switch topology, multiple hops are needed, and reducing hop counts awaits higher-port switches.

**Scale-Out:** per-accelerator Scale-Out is only 200 Gb/s with no uplift over two generations, and the switch silicon is also sourced externally.

In short, AWS lacks control over its fabric. Port counts, hops, and upgrade cadence are vendor-driven, leaving AWS with neither NVIDIA’s performance nor Google’s scale.

Competitively, this is a weak position. In the medium to long term, as Trn3 waits on UALink, Trn4’s fabric could fall further behind alternative vendor solutions.

![IMG_279](https://pub.pbkrs.com/cms/2026/0/JkjF6xXwDhh7p538qaSUjAyPb3JUFCPu.jpg?x-oss-process=style/lg)

**III. Where are the opportunities in AWS’s supply chain?**

As noted, AWS is not trying to beat NVIDIA, AMD, or Google outright. The question is where the supply chain opportunities lie.

**1) Is the fabric actually cheaper?**

AWS buys standard parts for the fabric, which likely avoids customization premiums. The domain-level NL72x2 (two racks) fabric cost is estimated as follows.

![IMG_280](https://pub.pbkrs.com/cms/2026/0/MfTx2L6ZUZxf4gdLTESBbg9mpk5gBKEg.jpg?x-oss-process=style/lg)

At first glance, the per-accelerator fabric cost looks favorable. The rack form factor roughly tracks GB300, yet unit fabric cost is lower.

Savings mainly come from fewer optics on the Scale-Out side, notably removing optics on the NIC-to-ToR hop. Trn3’s Scale-Out traffic first goes via AECs to two ToR switches at the rack top, so optics only appear above the ToR layer.

However, normalized for equal compute, the conclusion holds: Trn3’s fabric cost-performance is mediocre, and its competitiveness is limited.

![IMG_281](https://pub.pbkrs.com/cms/2026/0/iuGWgX2biA6j7FYREmWGU61UjcjLHvTQ.jpg?x-oss-process=style/lg)

![IMG_282](https://pub.pbkrs.com/cms/2026/0/hVYjsx55BniPQXotM45x2PJEyoiUpXSb.jpg?x-oss-process=style/lg)

![IMG_283](https://pub.pbkrs.com/cms/2026/0/Npw1umANDxmwjFDcBsQ15YATAA1hy4WZ.jpg?x-oss-process=style/lg)

**2) How to view supply chain opportunities?**

Buying standard parts lowers cost but also diversifies suppliers. This makes value capture and certainty along the chain critical for investors.

![IMG_284](https://pub.pbkrs.com/cms/2026/0/sfQwMHqX7gBAbQFyMNdfEAhxpHgQUxhP.jpg?x-oss-process=style/lg)

**By rack, copper interconnect carries the most value, followed by switches, optics, PCB, and PCIe retimers**. That is the current stack.

![IMG_285](https://pub.pbkrs.com/cms/2026/0/2rbeKkM3RhAsNk387Cxx5XMNiosoTp1x.jpg?x-oss-process=style/lg)

**For certainty, we look at iteration pathways.**

We see the strongest certainty in PCB. Regardless of Trn4’s direction, substrate requirements rise meaningfully.

\- If PCIe continues, generational upgrades raise requirements for substrates, retimers, and SerDes, with Gen7 especially demanding on materials. Only substrates are truly non-optional, while retimers are not strictly required and strong SerDes solutions (e.g., NVIDIA) can avoid them.

With improved PCB materials, some retimers could also be removed. That offers a path to cost/complexity reduction.

\- If Trn4 shifts to NVLink or UALink with 200G per lane, signals will need M9 or higher-grade materials. This further strengthens PCB certainty.

**Next in line are optics and copper.**

\- Large-scale fabrics elevate Scale-Out, boosting both the certainty and value of optics. This is a tailwind for optical interconnect vendors.

\- Copper will remain dominant for in-rack connections. AWS is a committed AEC adopter for cross-rack links, but it could still converge to industry norms and adopt optics for cross-rack in the future.

![IMG_286](https://pub.pbkrs.com/cms/2026/0/hfzXMCqkbn5uYCTHY233muJvvUnEAKET.jpg?x-oss-process=style/lg)

**Switches come after that.** During Trn3, AWS mainly buys standard parts, with Astera Labs as a key supplier for the switch tray. In the next-gen switch ASIC on the switch tray, AWS may pivot to Qualcomm. See our separate note for details.

For Trn4, if NVLink Fusion is adopted, switch silicon could depend on NVSwitch. If UALink is chosen, AMD could take the lead, with development involving Marvell and Astera Labs.

**Lastly, PCIe retimers.** Their value is modest and they can be substituted by better PCB materials, making them necessary today but potentially optimized out.

For detailed logic on optics, switches, and PCB supply chains, please refer to our earlier deep dives.

**3) Is copper out of runway?**

High-speed copper cables include DAC, ACC, and AEC. Versus DAC, ACC adds a redriver at the receive end to extend reach, while AECs add retimers at both ends to re-time signals.

This better compensates for copper loss and extends reach up to 30 m, as shown in the table.

![IMG_287](https://pub.pbkrs.com/cms/2026/0/4raspP7st5FYGYp1GEhmLfHja6K5Cime.jpg?x-oss-process=style/lg)

**The eye diagrams below highlight redriver vs. retimer differences.** The wider and cleaner the 'eye', the easier it is to distinguish 0s and 1s at the receiver.

After trace loss, the eye nearly closes (left). A redriver amplifies the attenuated signal and reopens the eye but also amplifies noise (middle), while a retimer samples, re-decodes, and re-transmits a clean signal (right).

![IMG_288](https://pub.pbkrs.com/cms/2026/0/D8YxDpik1AzZVpUipSaUKJmFUqvgv9UB.jpg?x-oss-process=style/lg)

At an industry level, Scale-Out is led by optics, while in-rack Scale-Up still favors DAC for its stability, efficiency, and cost. Copper’s base remains intact for now.

However, it is not rock solid: NVIDIA’s Kyber rack replaces in-rack copper with a PCB midplane, a negative for copper cables.

We see AEC as the growth area for copper, with two drivers. First, Scale-Up domains step out of a single rack but only span one or two adjacent racks, beyond DAC’s reach yet not worth moving to optics on power and reliability grounds, as with AWS’s cross-rack design.

Second, as per-lane speeds rise, DAC reach shrinks, forcing some former DAC links to upgrade to AEC. Over the longer term, as cross-rack distances extend, copper will hit limits.

For example, Rubin Ultra NVL576 spans eight racks and already plans to introduce optics.

![IMG_289](https://pub.pbkrs.com/cms/2026/0/5knTVWpK4Nbx4wtG3uavMe4sz1CrzE6h.jpg?x-oss-process=style/lg)

**4) The AEC value chain**

Upstream AEC value includes raw materials (copper and plastics), chips, cables, and connectors. We recommend focusing on high value-add AEC retimer chips and high-speed connector makers.

![IMG_290](https://pub.pbkrs.com/cms/2026/0/tUZn4MYcbTcUxyx5s89dhaWP62Lazd5c.jpg?x-oss-process=style/lg)

**1) Retimer chips:** Credo Technology dominates

Retimers account for the largest share of AEC value, and most of the profit accrues to the chip vendor. Credo holds over 80% share and, as AEC’s pioneer, is currently the only vertically integrated supplier offering both chips and finished cables.

Astera Labs ranks next, while Marvell and Broadcom are expanding. The landscape remains concentrated at the top.

![IMG_291](https://pub.pbkrs.com/cms/2026/0/SSCkURL5ZG1e7MWgH2aUiyCSNgmRVec7.jpg?x-oss-process=style/lg)

**2) High-speed connectors: global leaders guard the gate, domestic players are catching up**

This segment demands stringent conductivity and mechanical strength. Incumbents such as Amphenol and TE Connectivity have long led the field, working with chip partners like Credo to deliver end-to-end solutions from chips to assembly.

Facing the optics-over-copper trend, leaders like Amphenol and TE are acquiring to bolster optical capabilities. Competition is also broadening.

The connector market’s CR10 fell from 60% in 2013 to 50% in 2023, signaling more dispersed competition. Among Chinese vendors, Luxshare Precision has moved up to sixth by 2023, while Walracy and Zhaolong Interconnect are scaling.

![IMG_292](https://pub.pbkrs.com/cms/2026/0/P1i7ZH8CDi8bm1vaxRqZcnRbruumtg7g.jpg?x-oss-process=style/lg)

![IMG_293](https://pub.pbkrs.com/cms/2026/0/fDAxtPDEvV2SnFAeTkCJRBCa2tgZKZY4.jpg?x-oss-process=style/lg)

The core names referenced in this article are listed below (click here: [Dolphin’s interconnect basket](https://longbridge.cn/sharelist/40629976?app_id=longbridge&utm_source=longbridge_app_share&locale=zh-CN&share_track_id=62628a86-f451-4656-8705-7ee8bb5266a3&invite-code=032064)). For key names in optical modules, CPO, PCB and other interconnect hardware, see our earlier deep dives.

![IMG_294](https://pub.pbkrs.com/cms/2026/0/VERRsgWJb8fvvSJyMuKAiHVWLPdRy43P.jpg?x-oss-process=style/lg)

**Appendix**

![IMG_295](https://pub.pbkrs.com/cms/2026/0/pD5sFT6PJPj8dygrRmFgBtXu1du1YfF7.jpg?x-oss-process=style/lg)

![IMG_296](https://pub.pbkrs.com/cms/2026/0/2DXbYWQTxrcxc2cVqQiweHLV17aBn7is.jpg?x-oss-process=style/lg)

\<End>

[Risk Disclosure and Disclaimer: Dolphin Research](https://support.longbridge.global/topics/misc/dolphin-disclaimer)

**Dolphin Research AI DC interconnect series:**

**CPO industry**

[AI Hyper-Connect Era: Sprinting Toward Optics?](https://longbridge.cn/en/dolphin/post/41423680?channel=OWNN00110)['Copper' Isn’t Leaving Yet! CPO: Real Opportunity or Mirage?](https://longbridge.cn/zh-CN/dolphin/post/42139974?channel=OWNN00110)

**Fabric architecture**

[NVIDIA fabric: In the AI era, teaming 'over the net' beyond single chips — is there a China opportunity?](https://longbridge.cn/en/dolphin/post/43798848?channel=OWNN00110)

[AMD vs. NVIDIA in DC fabrics: Can Helios hold its own?](https://longbridge.cn/en/dolphin/post/43906382?channel=OWNN00110)

[Google fabric: Challenging NVIDIA’s dominance — what backs Google’s 'optical network'?](https://longbridge.cn/en/dolphin/post/43994983?channel=OWNN00110)

AWS fabric (Part I): ['AWS’s shortcuts: PCIe in a wrapper — can the fabric punch above its weight?'](https://longbridge.com/en/dolphin/post/44283715?channel=OWNN00110) 

**Single names**

[Lumentum (Part I): From optical interconnect veteran to 'omni water seller' — what’s the edge?](https://longbridge.cn/en/dolphin/post/44059432?channel=OWNN00110)

[Lumentum (Part II): Capacity crunch — what other trump cards remain?](https://longbridge.cn/en/dolphin/post/44191355?channel=OWNN00110)

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---
> **Disclaimer: This article is for reference only and does not constitute any investment advice.**