--- title: "CXMT Goes Vertical on Transistors: A No-EUV Catch-up Path — Can It Challenge the Memory Big Three?" type: "Topics" locale: "en" url: "https://longbridge.com/en/dolphin/post/44390427.md" description: "$CXMT(688825.SH) announced major breakthroughs in DRAM devices, 4F² cell architecture and hybrid bonding. Shares of the three leading overseas memory makers slumped on the headline.What the market fea..." datetime: "2026-10-16T12:14:25.000Z" locales: - [en](https://longbridge.com/en/dolphin/post/44390427.md) - [zh-CN](https://longbridge.com/zh-CN/dolphin/post/44390427.md) - [zh-HK](https://longbridge.com/zh-HK/dolphin/post/44390427.md) author: "[Dolphin Research](https://longbridge.com/en/dolphin.md)" generator: "portal-rs" --- # CXMT Goes Vertical on Transistors: A No-EUV Catch-up Path — Can It Challenge the Memory Big Three? $CXMT(688825.SH) announced major breakthroughs in DRAM devices, 4F² cell architecture and hybrid bonding. Shares of the three leading overseas memory makers slumped on the headline. What the market fears is clear: once a technical moat is cracked by a Chinese vendor, mass production can ramp fast. Because 4F² directly boosts bit output per unit area, the combination implies China DRAM effective supply could grow faster than previously expected. Two shifts drew the most attention: first, progress in switching the mainstream 6F² cell to a 4F² layout. Second, a self-developed VSG (Vertical Surrounded Gate) transistor to enable that architecture. The immediate implication of both is storage density. At the same process node, a 4F² cell is roughly one-third smaller than 6F², meaning about 50% more cells can fit in the same footprint, and DRAM unit output can rise materially. How much will this move the needle for the memory industry and the Big Three? To answer that, we need to make the technology legible first, and Dolphin Research will cover the following: 1) How are DRAM cells and arrays constructed, and what does today’s mainstream 6F² look like? 2) What changes when moving from planar to vertical surrounded-gate transistors, and from 6F² to 4F²? 3) Where are the hard problems in 4F², and is this unique to CXMT or an industry-wide direction? 4) What is the potential impact on the memory market and the Big Three? **Detailed analysis below:** **I. A single memory cell: the 1T1C structure** **1.1 1T1C: the capacitor stores data, the transistor acts as a switch** As a foundation, let’s briefly outline the lowest-level DRAM concepts. The smallest DRAM storage unit is the cell. **1T1C means one transistor plus one capacitor,** together storing 1 bit in the minimum cell. The topology is shown in the dashed frame below: **The capacitor is where data is actually 'stored',** with charge representing a binary value. Charge present denotes 1; no charge denotes 0. **The transistor serves as the switch,** controlling conduction between the capacitor and the bit line (the wire paired to each capacitor). When on, it allows write/read; when off, charge is retained in the capacitor. We will focus on the transistor, whose internal structure comprises the following parts. Together they determine how the word line controls conduction to enable charging and discharging. **Source and drain:** the two terminals of the transistor, one tied to the capacitor, the other to the bit line. Both are n-type doped silicon with abundant free electrons, hence conductive. **Substrate:** the p-type silicon between source and drain has few mobile electrons and is non-conductive by default, isolating the capacitor from the bit line. This default off-state blocks current without gate activation. **Gate and gate oxide:** the gate is a conductor located above the source/drain region, separated from silicon by a few-nm-thick insulator (gate oxide), and is connected to the word line. The word line drives a whole row of 1T1C switches. **Channel:** when a positive voltage is applied to the gate, the electric field attracts electrons to the silicon surface beneath the oxide, forming a conductive channel and turning on the path from source to drain. Remove the voltage and the channel vanishes, turning current off. With these parts working in concert, the word line toggles the transistor’s conductivity to charge or discharge the capacitor. That is how data is written and read. **1.2 Word lines and bit lines: assembling cells into arrays** A single cell stores only 1 bit, while a DRAM die contains tens of billions of them. They must be packed tightly yet be individually addressable for precise read/write. DRAM uses a row/column matrix: **cells form a grid connected by two perpendicular wiring sets—horizontal word lines select rows, vertical bit lines carry data.** This structure underpins addressing and operation. **Word line:** controls gate switching and ties together all transistor gates in a row. Driving a word line turns on the entire row while others remain off, i.e., it selects the row. **Bit line:** handles data write/read, tying together all drains in a column and thereby the capacitors. Each cell sits at a unique intersection of one word line and one bit line, mapping to row and column addresses. **Under this scheme, read/write/refresh works as follows:** **Write:** activate the target row’s word line to open the switches; drive the bit line high to charge the capacitor for a '1', or low to discharge for a '0', then deassert the word line. **Read:** when the transistor turns on, charge (if present) flows to the bit line and causes a small voltage change that is sensed as 0 or 1. Sense amplifiers then restore the signal. **Refresh:** reads consume some charge, and even with the switch off, leakage slowly drains the capacitor. Hence periodic read-and-rewrite cycles are required—this is why DRAM is 'dynamic'. Critically, leakage arises because the p-type substrate is not a perfect insulator even when the gate is off, allowing some electrons to seep through. Smaller capacitors also leak more easily. **The shorter the substrate channel, the higher the leakage and data-loss risk,** which limits further scaling of cell density and process precision. All else equal, higher density implies shorter channels. **II. From 6F² to 4F²: what changes?** **2.1 The 6F² physical layout: planar transistors** The connection topology is one thing; the physical layout on silicon determines cell area and thus bit output per wafer. That is the key economic driver. Today’s mainstream DRAM uses a 6F² layout with three vertical stacks: transistors and word lines at the bottom, bit lines in the middle, and capacitors at the top. See the illustration below. **First, transistors lie 'flat' on the wafer and come in pairs.** Oblique single-crystal silicon stripes (active areas) are arranged laterally and isolated by dielectric regions. Each stripe is crossed by two word lines (gates), forming two controllable transistor switches; the un-crossed part serves as a conductor. Thus, each active stripe connects to two capacitors, one per switch, while sharing a single bit line. This pairing helps packing efficiency. **Second, word lines are trenched into silicon, creating a U-shaped channel to curb short-channel leakage.** Rather than the textbook planar MOS, 6F² employs gate-in-trench to lengthen the channel without enlarging footprint. Despite the trench, the device remains laterally oriented. **Third, the relative placement of bit lines, word lines and capacitors differs vs. 4F²,** which we will detail in the next section. Layout drives spacing rules and density. *F stands for feature size, the minimum printable line/space of a given process. Advancing DRAM nodes (e.g., 1a, 1b, 1c) essentially means shrinking F.* *Node labels starting with '1' imply F is in the 10nm class, with a→c denoting smaller steps within that decade. Beyond that, '0a' denotes single-digit-nm class.* *Area efficiency is compared in multiples of F²: a 6F² cell occupies 6 squares of side F, while 4F² occupies 4 squares, abstracting away specific nodes.* **2.2 The transistor: from 'planar' to 'vertical + surrounded-gate'** **4F² starts by changing the transistor from a horizontal bar to a vertical pillar,** hence VSG—Vertical Surrounded Gate. This redefines the device geometry. The two main differences vs. the traditional switch are: it stands vertically instead of lying flat, and the gate surrounds the channel rather than sitting only above it. See the schematic below. **This structural shift drives several effects:** **First, channel length decouples from footprint.** In planar devices, source-channel-drain are laid out horizontally, so a longer channel consumes more area. In vertical devices, **channel length is set by pillar height** and is no longer tied to lateral area. To raise cell density, you no longer trade off by shortening channels, easing short-channel leakage constraints. **Second, stronger gate control cuts leakage and power.** A planar gate controls from one side, whereas a vertical pillar is fully wrapped, applying fields from all around for a tighter off-state. Lower leakage extends charge retention, reduces refresh frequency, and improves power and useful bandwidth. **Third, capacitors, bit lines, and word lines can be vertically stacked so the capacitor no longer must thread between bit lines.** In **6F²**, the flat transistor has two contacts pulled upward: one to the bit line layer and another through that layer to the top capacitor. Thus the capacitor contact must pass through the gap between adjacent bit lines, forcing larger bit-line pitch. In **4F²**, the three stack on the same vertical axis: bit line below the pillar, gate wrapping the midsection, capacitor on top. The capacitor contact no longer squeezes between bit lines, directly shrinking cell area. **2.3 Architecture: from 6F² to 4F², up to ~50% more bits per area** **DRAM scaling aims to pack more cells per area while keeping charge retention and read reliability.** Two limits emerge: transistor leakage and capacitor capacity. Further shrink reduces capacitor area, forcing more height and extreme aspect ratios, which complicates etch/deposition and hurts yield. **4F² sidesteps this by architecture, shrinking cell area without shrinking F.** In **6F²**, the capacitor contact must pass between bit lines, so **bit-line pitch is relaxed to 3F** while word-line pitch is 2F, yielding **2F × 3F = 6F²**. Layout rules, not just litho, set the limit. In **4F²**, the capacitor aligns above the pillar, freeing the bit-line spacing to the minimum **2F**, so **cell area becomes 2F × 2F = 4F²**. At the same node, that is roughly one-third smaller than 6F², as seen in the top views below. The same area can host roughly 50% more cells, with three immediate impacts. **First, array density jumps, but whole-die gains are diluted.** At fixed F, a 4F² cell is 2/3 the area of 6F², so a given area holds 1.5x cells, i.e., **array density can rise by up to ~50%**. However, a DRAM die also includes sense amps, decoders and drivers whose area does not scale with the cell change. As cells get denser, fitting periphery beside arrays gets harder, so die-level capacity gains will be below 50%. Media reports of a '**\~30–50% per-die density uplift**' reflect this haircut. This is also why the industry favors putting periphery on another wafer and stacking via hybrid bonding under the DRAM array. Only then can the array-level density dividend translate to the die; CXMT’s push for 'DRAM/CMOS decoupling + wafer-level hybrid bonding' targets exactly this. **Second, design rules relax in one step, lowering EUV dependency.** Architectural gains deliver density without tighter F, which otherwise requires more advanced litho. UBS estimates first-gen 4F² relaxes critical dimensions by ~30%, akin to skipping roughly two nodes. UBS also expects the first 4F² node’s capacitor feature sizes to be comparable to 1c. For CXMT, which lacks EUV under export controls, this is pivotal: **pushing 6F² further leans on EUV or more complex multi-patterning,** while **4F² secures density without narrower lines.** **Third, capacitor process pressure eases.** Late-stage 6F² shrink forces ever taller, higher-aspect-ratio capacitors to maintain charge, stressing etch/ALD and yield. With looser rules, capacitors need not be as 'needle-like', reducing high-AR challenges. That said, **the 6F²→4F² shift is a one-off dividend.** Beyond the first 4F² gen, **vendors must still shrink F to advance nodes,** bringing litho back to center stage. Roadmaps reflect this inevitability. Per The Elec in Apr, Samsung plans to run 4F² across 10a/10b/10c before moving to 3D DRAM, so later nodes still need finer F and advanced litho. Korean media in Sep reported Samsung and SK hynix both target High-NA EUV in DRAM mass production around 2028. To wrap up Part 1: the shift from 6F² to 4F² is not about printing finer lines. By standing the transistor upright and wrapping the gate around it, the channel length no longer competes with cell area for space, and the capacitor, bit line and word line can finally be stacked in one vertical column instead of weaving around each other. That alone shrinks the cell by about a third, roughly 50% more bits per unit of array area at the same node. For CXMT, locked out of EUV, this is the point: density bought with architecture rather than lithography. But a one-time bonus is not a free pass. How hard is 4F² to actually build, where do Samsung, SK Hynix and Micron stand, and what does this mean for memory prices and profits? That is Part 2: [\[link\]](https://longbridge.com/en/dolphin/post/44428930). \ Risk disclosure and disclaimer: [Dolphin Research Disclaimer and General Disclosure](https://support.longbridge.global/topics/misc/dolphin-disclaimer) ### Related Stocks - [688825.CN](https://longbridge.com/en/quote/688825.CN.md) --- > **Disclaimer: This article is for reference only and does not constitute any investment advice.**