After the fact that Moore's Law has actually become obsolete, the previous way of improving chip performance by enhancing the process gradually became a thing of the past. Instead, various advanced packaging technologies have taken over, using various &#34;splicing&#34; methods to enhance chip performance. A typical example of this trend is the practice of GPU chip giant NVIDIA on its latest B200.
As a staunch supporter of single-chip technology, NVIDIA has been improving chip performance through process and architecture enhancements for many years. However, on the B100, NVIDIA actually adopted the industry-promoted Chiplet design approach, connecting two chips that have exceeded the reticle limit using their own NV-HBI (Nvidia High Bandwidth Interface). According to technews, this is backed by TSMC's advanced CoWoS packaging technology.
In fact, since NVIDIA introduced HBM and LLM in GPUs, advanced packaging has gained great popularity in high-performance computing. For example, the shortage of H100 supply due to TSMC's shortage of CoWoS advanced packaging process capacity last year sparked widespread discussions in the industry. The continuous increase in chip performance requirements has also driven the continuous upgrading of advanced packaging technology, prompting more contemplation on the development path of advanced packaging:
For example, how will TCB (Thermocompression bonding) and hybrid bonding develop?
<h2>TCB, still viable?</h2>
Before discussing TCB in detail, let's first define advanced packaging. In fact, different industries have different definitions of what advanced packaging is. Semianalysis analyst Dylan Patel defines all packages with bump sizes smaller than 100 microns as &#34;advanced packaging.&#34;
He further points out in the article that the most common type of advanced packaging is called Fan-out, which became widely known after Apple applied it to its A-series mobile chips. Compared to traditional flip-chip packaging, the bump density of Apple chip packaging is about 8 times higher. In terms of structure, in addition to conventional packaging, advanced packaging now includes 2.5D and 3D packaging.
So-called 2.5D / 3D packaging are two packaging methods that include multiple ICs in the same package. In a 2.5D structure, two or more active semiconductor chips are placed side by side on a silicon interposer to achieve a very high chip-to-chip interconnect density
In a 3D structure, active chips are integrated through chip stacking to achieve the shortest interconnection and the smallest package size.
Currently, 2.5D is the preferred choice for more chip manufacturers. For example, NVIDIA's H100 GPU uses the most common and highest-yield TSMC CoWoS (chip on wafer on substrate) in 2.5D packaging. In this packaging method, TSMC encapsulates the active chips on the top of the wafer with only interconnections and microbumps, and then uses traditional methods to package this stack of chips onto the substrate. The popular HBM in recent years is another typical example of 2.5D packaging, which also uses the key technology discussed in this chapter - TCB.
As a mainstream method of wire bonding, TCB was developed by three scientists, O. L. Anderson, H. Christensen, and P. Andreatch, at Bell Labs between 1955-58.
According to related information, thermocompression bonding is mainly used to create atomic-level metal bonding. It uses force and heat to promote the migration of atoms between lattices, thereby forming clean, highly conductive, and strong bonds. Typically, TCB is used for CMOS processes of vertical integrated devices, compliant bonding between gold wires and surfaces, inverted chip applications for bonding chip bumps to substrates, and thermocompression bonding for connecting micro components.
Due to its leading applications, there has been a high demand for this type of packaging after its release. This technology has also been dominating the packaging market for the past few decades. Even the HBM mentioned at the beginning of the article, whether supplied by Samsung, SK Hynix, or Micron, all use TCB technology.
As an innovative type of DRAM, HBM has shone brightly in the past few years. Even NVIDIA CEO Jensen Huang mentioned HBM as a technical miracle at the recent GTC conference.
From a technical perspective, HBM is a way to increase memory bandwidth above traditional DRAM. It achieves this by using wider memory buses. These wide buses can create issues related to IO counts, but HBM is designed from scratch to coexist within the same package, thus overturning the IO issue and allowing for tighter integration
According to Semianalysis analyst Dylan Patel, the reason why current HBM still uses TCB is because this technology solves several main issues of standard flip chip. For example, heat is applied from the top of the chip, so only the connection between the chip and the C4 solder will heat up, which can minimize any substrate warping issues to the maximum. At the same time, this bonding method ensures uniform adhesion without any gap variations or tilting; finally, this bonding has almost no gaps and no contamination.
&#34;At the same IO spacing, TCB can achieve better electrical performance. TCB also allows for IO spacing to be reduced to smaller sizes. TCB can also package thinner dies and packages. The latter is the reason why HBM uses TCB. Compared to the standard flip chip process, TCB seems to be a better technology,&#34; Dylan Patel continued.
As one of the earliest manufacturers to create TCB solutions, Mr. Zhang Zanbin, Executive Vice President and General Manager of Kulicke &amp; Soffa, also told the semiconductor industry observer: &#34;For a long time to come, TCB will play a very important role in AI, HPC, and large chips, mainly due to its cost advantages.&#34; &#34;Currently, most chips have a pitch of 50 microns and 30 microns, with the narrowest being 25 microns. We believe TCB can achieve below 10 microns, so there is still a long way to go,&#34; Zhang Zanbin added.
Taking HBM as an example, Zhang Zanbin stated that there are currently two implementation methods for HBM: one is to package it with traditional flip chips. The other is to use TCB. The former will always exist, but if temperature control is needed, TCB is used. Additionally, because the stacked dies of HBM need to be very thin, even the most advanced 12-stack HBM currently still uses TCB technology. &#34;From the current perspective, the next generation 16-stack HBM will still use TCB technology,&#34; Zhang Zanbin told the author.
In his article, Dylan Patel revealed that most of Intel's packaging technologies also use TCB and have become strong supporters of TCB. Intel uses TCB in many packaging applications. And because TCB is the best technology for packaging ultra-thin chips, TCB has also been experimented with in flagship devices for mobile applications using OSAT and IDM packaging. Samsung, Qualcomm/Amkor have also used TCB in some applications related to stacked packaging (PoP) DRAM, and OSATs have begun ordering more and more TCB tools
But as Dylan Patel said, manufacturers are turning to more magical hybrid bonding technology.
<h2>Hybrid Bonding, a Promising Future</h2>
According to Dylan Patel, the last major paradigm shift in the packaging industry was from wire bonding to flip-chip. Since then, more advanced packaging forms (such as wafer-level fan-out and TCB) have been progressive improvements based on the same core principles. These packaging methods all use some form of soldered bumps as interconnects between silicon and packaging or board, and these technologies can be scaled down to gaps of about 20 microns.
&#34;However, to further expand, we need another paradigm shift: adopting hybrid bonding with non-bump interconnects, exceeding 10 microns in size, with a roadmap to the 100-nanometer range, and without the use of any intermediaries such as solder with higher resistance.&#34;
The so-called hybrid bonding refers to bonding both dielectric and metal bond pads in a single bonding step. Specifically, there are two types of hybrid bonding: wafer-to-wafer (W2W) bonding, which is more mature but limits combinations of chips of the same size; and die-to-wafer (D2W) bonding, which involves more process steps and placing chips individually on carrier wafers or glass (collective chip-to-wafer method).
In both cases, both wafers processed with BEOL metallization undergo bonding dielectric CVD, barrier layer deposition, copper filling, dielectric planarization (with slight copper recess), plasma activation for bonding preparation, alignment, room temperature bonding, and annealing to form copper bond pad electrical connections. The silicon wafer backside is then ground to final thickness (usually &lt;100nm), followed by dicing, and then final assembly and packaging.
The transition to hybrid bonding is quite simple compared to microbumps. The reason is that 3D memory stacks and heterogeneous integration (two participants beyond the Moore era) require high interconnect density, as mentioned above, and hybrid bonding can meet this requirement. Compared to microbumps that inherently support high-density interconnect solutions, hybrid bonding can provide smaller I/O terminals and reduced interconnect spacing. The distance between each chip depends on the height of the microbumps, but in hybrid bonding, this distance is almost zero.
Therefore, hybrid bonding interconnect solutions can significantly reduce overall package thickness, potentially up to several hundred microns in multi-chip stack packages. As a result, since its first appearance in CMOS image sensors over a decade ago, hybrid bonding has gradually moved towards 3D NAND, and even DRAM and HBM have shown interest in hybrid bonding
In February this year, there was news that Intel's next-generation Xeon &#34;Clearwater Forest&#34; CPU will adopt a hybrid bonding 3D stacking technology called &#34;Foveros Direct&#34;.
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/393fe678-2bb4-426f-8290-79c2e0540072.png?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/393fe678-2bb4-426f-8290-79c2e0540072.png"/>
Some TCB supporters admitted that after the bump pitch reaches 25 microns, the installed TCB tools will continue to be used. Zhang Zanbin also believes that Hybrid Bonding will only be used in very high-end applications.
&#34;Hybrid Bonding is for high-end processes like nanometers. This technology is not applicable to every product because its price and cost are very high. So I think only a few high-end products will have this application, and most chips will still use traditional methods,&#34; Zhang Zanbin said. He pointed out that unlike TCB, which is a back-end process, hybrid bonding is to some extent a front-end process, so the challenges it brings are also obvious.
&#34;Hybrid bonding has very high environmental requirements, requiring a class 1 clean room (very clean). That's why most of the current customers investing in Hybrid Bonding are front-end customers because they have front-end processes, equipment, and environments, so they can expand Hybrid Bonding. However, if a traditional packaging factory wants to enter this field, it needs to make a large investment to create a very clean clean room, which raises the threshold significantly. That's why wire bonding machines are still so popular today because they are the most practical and cheapest method in packaging,&#34; Zhang Zanbin explained.
A recent piece of news has also dealt a blow to hybrid bonding.
At IEDM 2023 held in December last year, SK Hynix announced that it has ensured the reliability of the hybrid bonding process used in HBM manufacturing. The news stated that the standard thickness of HBM chips is 720 µm. The 6th generation HBM (HBM4) expected to be mass-produced around 2026 will need to vertically stack 16 DRAMs, posing a challenge to current packaging technologies to meet customer satisfaction. Therefore, the application of the Hybrid Bonding process in the next generation of HBM is considered inevitable by the industry.
However, earlier reports revealed that the main participants of the Joint Electron Device Engineering Council (JEDEC) recently agreed to set the standard for HBM4 products at 775 microns, which means that HBM developers can fully achieve 16-layer DRAM stacking HBM4 using existing bonding technologies.
Nevertheless, this is unlikely to deter manufacturers from entering this race. It is understood that companies including TSMC, Intel, Samsung, SK Hynix, Micron, Sony, Howie Technology, Kioxia, Western Digital, Besi, Shibaura Electronics, Tokyo Electronics, Applied Materials, EV Group, SUSS Microtec, SET, and Bosch, among others, have shown interest in hybrid bonding
Even the main supplier of TCB solutions, Kulicke &amp; Soffa, has joined the hybrid bonding camp and conducted pre-research on this technology, believing that this technology will bring new opportunities at some point in the future.
<h2>Equipment manufacturers, responding to challenges</h2>
Although there have been twists and turns, the path of advancement in advanced packaging is irreversible.
Industry consulting firm Yole stated in a report released at the end of last year that the advanced packaging market is expected to decline by 1.4% in 2023. However, in Q3 2023, the revenue of advanced packaging (AP) increased significantly by 23.7% compared to the previous quarter, reaching a total of 11 billion USD.
Yole further pointed out that in the coming years, the revenue of advanced packaging is expected to grow at a compound annual growth rate of 8.6%, increasing from 429 billion USD in 2022 to 704 billion USD in 2028. In terms of revenue, flip-chip BGA, flip-chip CSP, and 2.5D/3D are the dominant packaging platforms, with 2.5D/3D technology showing the highest growth rate, expected to increase from 9.4 billion USD in 2022 to 22.5 billion USD in 2028, with a compound annual growth rate of 15.6%.
As the main implementers of advanced packaging, equipment manufacturers are also responding to challenges.
First, let's look at Kulicke &amp; Soffa. As mentioned above, they should be very optimistic about TCB at this stage. In August last year, they announced that they would expand their cooperation with UCLA CHIPS to develop ultra-fine pitch micro-bump interconnect solutions. According to their press release at the time, shortly thereafter, the thermal compression bonding (TCB) with a 30μm micro-bump pitch became feasible. By leveraging formic acid treatment, K&amp;S demonstrated the ability to achieve a 10μm pitch in TCB. The collaboration aims to further develop a manufacturable copper-to-copper solution, reducing the pitch to below 5μm.
Robin Ng, CEO of ASMPT, stated in a media interview that he will start providing hybrid bonding machines to customers in the second half of this year. Ng mentioned that when mass production of hybrid bonding chip system packaging truly takes off, ASMPT is ready to deliver the machines. He further indicated that ASMPT will significantly increase the R&amp;D budget for advanced packaging, including thermal compression bonding, photonics, and hybrid bonding.
As a proactive player in the hybrid bonding machine market, Richard Blickman, CEO of Besi, revealed during the annual performance introduction that by 2023, in addition to the existing three customers, the company has won six new customers for these hybrid bonding machines. Besi has also deployed more than 40 sets of hybrid bonding systems in the market
According to relevant information, Intel and TSMC are the main customers of Besi, but they have high expectations for the memory market. For example, HBM is the direction that Besi is most optimistic about, but currently they only have Micron as a customer. Richard Blickma predicts that the memory market will not deploy hybrid bonding for the first generation of HBM4, with a higher possibility for the second generation.
Another equipment supplier, EV Group, provides equipment for the NAND market to achieve wafer-to-wafer hybrid bonding processes.
<h2>Conclusion</h2>
In the view of analysts, many packaging technologies will be used in parallel in the future. Hybrid bonding will not replace TCB, but will complement each other.
Currently, system developers such as Apple, AMD, Nvidia, and Intel are researching both, and the proportion of foundries and logic and memory manufacturers adopting these two interconnection options remains to be seen. The situation may vary greatly among different customers. For example, AMD has already used hybrid bonding in its microprocessors, while Nvidia has chosen TCB. Both technologies are still in development.
If the pitch is reduced to below 25 microns, hybrid bonding is undoubtedly an important choice, but it is more expensive.
In conclusion, technology is always advancing, and we can always find solutions.
Author: Li Shouping, Source: Semiconductor Industry Observation, Original Title: &#34;Will Hybrid Bonding Replace TCB?&#34;

NVDA

SOXL

NVDL

Hybrid bonding will not replace TCB, but will complement each other. After the failure of Moore's Law, advanced packaging technology has become the main way to improve chip performance. NVIDIA adopts Chiplet design on B200, relying on TSMC's advanced CoWoS packaging technology. The continuous advancement of advanced packaging technology has driven the development of TCB and hybrid bonding. Advanced packaging is defined as packaging with die size smaller than 100 microns, with widespread application of fan-out packaging

Will hybrid bonds replace TCB?