---
title: "Advanced Semiconductor Engineering launches CPO energy efficiency solutions targeting AI data center applications"
type: "News"
locale: "en"
url: "https://longbridge.com/en/news/234144352.md"
description: "Advanced Semiconductor Engineering has launched Co-Packaged Optics (CPO) components aimed at reducing power consumption and meeting the application demands of artificial intelligence (AI) data centers. This technology integrates multiple optical engines with ASIC chips within a single package, shortening electrical connection paths, reducing insertion loss, and enhancing data throughput. Advanced Semiconductor Engineering emphasizes that the CPO design can significantly improve system bandwidth density to meet the growing demands of AI, cloud, and edge computing data centers"
datetime: "2025-04-02T02:36:31.000Z"
locales:
  - [zh-CN](https://longbridge.com/zh-CN/news/234144352.md)
  - [en](https://longbridge.com/en/news/234144352.md)
  - [zh-HK](https://longbridge.com/zh-HK/news/234144352.md)
---

# Advanced Semiconductor Engineering launches CPO energy efficiency solutions targeting AI data center applications

The packaging manufacturer Advanced Semiconductor Engineering has launched Co-Packaged Optics (CPO) components, which can directly integrate multiple Optical Engines (OE) and Application-Specific Integrated Circuits (ASIC) into a single package, reducing power consumption and targeting artificial intelligence (AI) data center applications.

Advanced Semiconductor Engineering stated today in a press release that as AI technology applications become more widespread, energy-saving and reduced power consumption design requirements are increasing. The design of Advanced Semiconductor Engineering's CPO components utilizes advanced packaging technology to directly integrate the optical engine into the switch, shortening the electrical connection path, reducing insertion loss, and thereby improving power consumption.

In addition, the CPO packaging process of Advanced Semiconductor Engineering includes controlling substrate warpage and coplanarity, which can technically respond to the structural design and technical requirements of optical fiber components, enhancing data throughput to meet the design needs of AI data centers.

Regarding integration technology, Advanced Semiconductor Engineering pointed out that the CPO solution integrates multiple optical engines and ASIC chips. The CPO technology platform can integrate processors (CPU), graphics processing units (GPU), and customized computing architectures (XPUs) with optical components in a single co-packaged solution, enhancing the performance of high-speed optical data links.

Hong Zhibin, Deputy General Manager of R&D at Advanced Semiconductor Engineering, explained that placing the optical engine very close to the ASIC chip reduces connection loss and eliminates the need for retiming chips to compensate for the signals between the two, which can lower energy consumption and significantly increase the overall bandwidth density of the system.

Advanced Semiconductor Engineering noted that the increasing demand for data centers driven by advanced AI, cloud, and edge computing applications poses challenges for chip power and cooling technologies. The company continues to lay out silicon photonics (SiPh) technology and CPO solutions to meet the advanced packaging needs of key chips for AI data centers

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