According to the Zhitong Finance APP, Wall Street financial giant Morgan Stanley recently released a research report stating that TSMC (TSM.US), the &#34;king of chip foundry,&#34; has initiated the construction of a 310 mm² Panel-Level chiplet advanced packaging pilot line (i.e., CoPoS advanced packaging system). This has prompted semiconductor equipment and advanced packaging giants like ASE to synchronize the FOPLP size reduction to 300/310 mm², indicating that the &#34;wafer-level CoWoS to panel-level CoPoS advanced packaging&#34; super upgrade iteration has officially entered the investment and preliminary pilot manufacturing phase.
The launch of the CoPoS pilot line by TSMC signifies that this chip manufacturing giant is officially initiating a &#34;major transformation in advanced packaging&#34; that covers the entire upstream to downstream industry chain of chips. CoPoS will primarily be used to address the capacity bottlenecks of CoWoS advanced packaging on a large scale, as well as the cost issues in the initial wafer production and the entire manufacturing to packaging process, targeting the next generation of AI training/inference AI GPUs/AI ASICs, pursuing larger scale chiplet die and higher HBM stacking numbers in a single package to achieve exponential performance improvements and potentially reduce the cost of expanding capacity compared to CoWoS.
Morgan Stanley's global chip industry chain research data shows that TSMC has invested in the construction of the CoPoS 310mm² pilot line, while ASE almost simultaneously announced the adoption of 300 mm² panel 2.3D packaging technology (FOCoS-Bridge), indicating that the advanced packaging industry is accelerating its transition to 310 mm². In June 2025, a large number of semiconductor equipment and raw material exhibits related to PLP/CoPoS also appeared at the Japan Electronic Packaging Society (JIEP) seminar. The Morgan Stanley report indicates that the industry expects large-scale CoPoS-related semiconductor equipment delivery and installation debugging by mid-2026, process rollout in 2027, and a large-scale equipment investment decision period by mid-2027, along with initial wafer production.
The CoPoS advanced packaging system draws on the silicon-to-silicon technology stack of CoWoS but has made system-level adjustments in substrate form, high-end semiconductor equipment chain, and yield bottlenecks, providing a stronger performance ceiling and more easily expandable capacity to meet the increasingly large global AI computing power demand.
For AI/HPC super clients like NVIDIA, AMD, Broadcom, and Marvell Technology, CoPoS offers larger scale advanced packaging I/O and HBM stacking numbers, greatly alleviating the supply-demand imbalance in advanced packaging capacity and the high costs of initial wafer production and chip manufacturing. From the perspective of &#34;performance ceiling,&#34; the panel-level area + HBM stacking combination of CoPoS can provide greater bandwidth/capacity expansion than the current CoWoS advanced packaging, thus offering a higher performance ceiling for AI chips focused on ultra-large model training/inference systems.
From the perspective of performance growth and valuation expansion, the entire chip industry chain is expected to experience significant growth. For NVIDIA, AMD, and the three major EDA giants, there is potential to drive larger-scale terminal demand through supply-side product updates and iterations, especially for AI chip leader NVIDIA, which is expected to meet the &#34;starry sea&#34; of AI computing power demand to a greater extent; the high-end semiconductor equipment and chip raw material chain is about to welcome a new round of super-large-scale equipment capital expenditure due to the panelization of CoPoS, particularly for laser cutting, panel lithography, and vacuum bonding
The world's top semiconductor equipment manufacturers in fields such as dry film packaging focus on key equipment like Panel-level direct-write lithography, laser cutting, and panel mounting.
From Wafer to Panel: TSMC Leads the &#34;CoPoS Revolution&#34;
The CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging process focuses on completing re-routing and TSV on a 300mm wafer silicon interposer first, then mounting logic/storage bare chips on top, and finally bonding them to BT/ABF organic substrates. Due to the limited effective area of the wafer, after occupying space with a large core chip and multiple HBM, the single wafer output is only 3-4 chips, and the yield decreases with area, ultimately leading to higher costs per chip, long-term capacity constraints, and performance ceilings being reached.
The CoPoS (Chip-on-Panel-on-Substrate) process focuses on moving the silicon interposer or re-routing layer to a rectangular panel (typically 310 mm × 310 mm), first processing a large area embedded silicon RDL, then mounting core chiplet/HBM, and finally assembling with the organic substrate. CoPoS aims to package more chiplet cores and achieve higher HBM stacking, targeting 1nm and below ultra-advanced processes and the next generation of AI chip performance leaps. However, warping and edge coating uniformity present new challenges.
Therefore, panels based on CoPoS have high utilization, with a single board area approximately 3-5 times that of a wafer, combined with potential capacity increases of 2-3 times and a cost reduction of about 20-30% per unit area, the semiconductor equipment chain may need to be re-adapted (mainly focusing on large laser cutting, direct imaging lithography, and vacuum mounting machines).
Morgan Stanley stated that for the chip industry chain, transitioning from 12-inch wafer-level equipment to PLP-related raw materials and equipment represents a new super-large-scale CAPEX cycle, with semiconductor equipment giants (such as Disco, Ulvac, Screen HD, and Canon) expected to receive incremental orders, marking a significant structural growth opportunity.
CoPoS and AI Computing Power
With the global popularity of ChatGPT and the heavyweight launch of the Sora text-to-video model, combined with Nvidia's unparalleled performance over several quarters in the AI field as a &#34;shovel seller,&#34; it signifies that human society has entered the AI era. At Nvidia's earnings meeting at the end of May, Jensen Huang optimistically predicted that the Blackwell series would set the strongest AI chip sales record in history, driving the artificial intelligence computing power infrastructure market to &#34;exhibit exponential growth.&#34; &#34;Now, every country views AI as the core of the next industrial revolution—a new emerging industry that continuously produces intelligence and critical infrastructure for every global economy,&#34; Huang stated during the earnings discussion with analysts.
The AI computing power demand brought by inference is described as &#34;starry seas,&#34; expected to drive the artificial intelligence computing power infrastructure market to continue showing exponential growth, with &#34;AI inference systems&#34; being the largest source of future revenue for Nvidia, according to Huang
In the unprecedented competition for &#34;bandwidth-computing power&#34; AI infrastructure centered around AI chips, wafer-level CoWoS has advanced NVIDIA's AI GPU packaging to the limit of at least 6 HBM memory systems, with a total bandwidth of 3.9 - 4.8 TB/s, for example, CoWoS-S is limited to a silicon interposer size of 120 × 150 mm.
On the other hand, panel-level CoPoS, by enlarging the carrier area to a typical 310 × 310 mm, can accommodate up to 10-12 next-generation HBM—HBM4 and more chiplets, with a theoretical peak bandwidth expected to exceed 13-15 TB/s, and storage capacity at least doubled. The larger panel specifications allow for more extensive packaging integration of GPU/CPU chiplets, optical I/O dies, and dedicated AI acceleration IP, exponentially shortening interconnections and significantly reducing overall latency and power consumption. Therefore, in terms of the performance of the next-generation AI chips and meeting computing power demands, CoPoS provides a much broader &#34;performance ceiling,&#34; meeting computing power needs over a larger range.
In other words, as the demand for AI computing power and the parameter scale of AI models continue to grow explosively, even with HBM stacked to more than 10 chips, advanced CoPoS packaging will fully unleash the advantages of panel area, leading to significant improvements in the performance of AI chips and other AI computing power infrastructure, as well as a decrease in the cost per unit of computing power. For example, when the usable area of the CoPoS panel reaches more than five times that of a single CoWoS, combined with HBM4 (1.6 TB/s/stack, 2048-bit total bus), 12 stacks can achieve a peak of over 19 TB/s—meaning the bandwidth ceiling exceeds four times that of the current theoretical CoWoS

Taiwan Semiconductor has launched a 310 mm² Panel-Level chiplet advanced packaging trial line CoPoS, marking a transformation in packaging from CoWoS to CoPoS. This move aims to address the capacity bottlenecks and cost issues of CoWoS, particularly in response to the demand for AI GPUs and ASICs. A report from Morgan Stanley indicates that large-scale equipment deliveries are expected to be realized by 2026, with the investment decision period entering in 2027

- Morgan Stanley reports that TSMC has initiated the construction of a 310 mm² Panel-Level chiplet advanced packaging pilot line, marking a significant shift in semiconductor packaging technology.  
- This CoPoS system aims to address capacity bottlenecks and cost issues in advanced packaging, particularly for next-generation AI chips, while enhancing performance and reducing costs compared to existing methods.  
- The transition to CoPoS is expected to drive substantial growth in the semiconductor industry, benefiting major players like NVIDIA and AMD as they meet the increasing demand for AI computing power.

From CoWoS to CoPoS: TSMC is initiating a "advanced packaging revolution" sweeping the chip industry chain