---
title: "The \"Red and Blue Factory\" dominated server CPUs welcome new forces! NextSilicon challenges Intel and AMD with RISC-V architecture"
type: "News"
locale: "en"
url: "https://longbridge.com/en/news/262362711.md"
description: "Israeli chip startup NextSilicon has launched a central processing unit based on the RISC-V architecture, aiming to challenge the server CPU market dominated by Intel and AMD. Its new CPU has been evaluated by the U.S. national laboratories and claims to be faster, more energy-efficient, and requires no code changes. NextSilicon has raised approximately $300 million in funding, and its flagship product \"Maverick-2\" is designed to accelerate precision scientific computing tasks, competing with NVIDIA's HPC computing clusters in the future"
datetime: "2025-10-23T07:15:35.000Z"
locales:
  - [zh-CN](https://longbridge.com/zh-CN/news/262362711.md)
  - [en](https://longbridge.com/en/news/262362711.md)
  - [zh-HK](https://longbridge.com/zh-HK/news/262362711.md)
---

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# The "Red and Blue Factory" dominated server CPUs welcome new forces! NextSilicon challenges Intel and AMD with RISC-V architecture

According to the Zhitong Finance APP, NextSilicon, a chip startup based in Israel, has announced that its newly launched CPU-type open-source architecture computing chip is undergoing comprehensive evaluation by the U.S. National Laboratories. The company stated on Wednesday Eastern Time that it is developing a central processing unit (CPU) based on the open-source instruction set architecture (ISA) - RISC-V architecture. The management expects this CPU to challenge the "red and blue" chip giants dominating the data center server CPU market, namely AMD and Intel, and also hopes this CPU will help NextSilicon compete with NVIDIA's HPC computing clusters launched for data centers.

In the future, Intel's (blue factory) and AMD's (red factory) x86 architecture server CPU product lines, as well as NVIDIA's Grace CPU developed based on ARM architecture, will undoubtedly face a new competitor for a long time.

It is understood that NextSilicon has raised approximately $300 million in financing, and its flagship chip product - the "Maverick-2" data flow accelerator is designed to significantly accelerate precision scientific computing tasks, such as nuclear weapon modeling and supersonic missiles. This field has been fully dominated by NVIDIA, but in recent years, as NVIDIA has completely shifted its focus to low-precision large computing tasks like artificial intelligence, startup chip companies like NextSilicon have attempted to fully leverage the shift in focus of this AI super giant, which has long ranked first in global market capitalization.

On Wednesday Eastern Time, NextSilicon revealed significant information for the first time, indicating that the company is currently developing a supplementary data center server CPU product in the form of a new central processing unit, while this server CPU market is still fully dominated by Intel and AMD. NextSilicon employs a technology called RISC-V open-source architecture, which is an open computing architecture standard primarily competing with ARM architecture and is increasingly being adopted on a large scale by chip giants like NVIDIA and Broadcom.

It is understood that the "AI chip leader" NVIDIA often pairs its GPU chip product line with its own or third-party central processing platforms (CPUs), and even collaborates with competitors like Intel to achieve tighter coupling between these two types of chips.

**Challenging the traditional "x86+GPU" instruction stream combination**

The essence of the Maverick-2 launched by NextSilicon is a "data flow/reconfigurable" accelerator (NextSilicon refers to it as Intelligent Compute Architecture, a non-Von Neumann paradigm). The main computing array is not a general-purpose RISC-V architecture computing unit, but the company has embedded multiple RISC-V cores within the chip and advanced packaging system to run those serial code paths and control tasks that are difficult to parallelize but must be executed at high speed NextSilicon's official statement and technical media reports emphasize that the computing unit of Maverick-2 operates in a runtime reconfigurable graph/data flow manner, which is not equivalent to traditional CPU/GPU instruction stream architectures. NextSilicon also highlighted that Maverick-2 integrates self-developed RISC-V cores (with up to dozens of E-cores) to handle serial segments.

Currently, NextSilicon states that its plan for mass production of server CPUs is still a test chip. However, its main chip product line—Maverick-2 and the more advanced acceleration series chips—has entered the actual mass production stage. NextSilicon claims it can execute some of the same types of computing tasks as NVIDIA's GPU chip product line at a faster speed and lower power consumption without the need to completely rewrite the software code used.

The "host + accelerator" supercomputing node composed of Maverick-2 and the upcoming mass-produced RISC-V architecture CPU is not equivalent to the traditional CPU + GPU instruction stream architecture. For HPC supercomputing centers and scientific computing data center loads, this combination from NextSilicon can provide better cost-effectiveness and energy efficiency compared to similar data center combinations from Intel and AMD.

It is understood that the comprehensive research institution Sandia National Laboratories in the United States has been evaluating prototype computing systems built with NextSilicon chips for three years.

James H. Laros III, a senior scientist at Sandia National Laboratories and the Vanguard project leader, stated in a statement that the "performance results of NextSilicon chip products are impressive, demonstrating the true potential to significantly enhance our laboratory's complex computing capabilities without the overhead of extensive software code modifications."

**Open Source Architecture—RISC-V Architecture Accelerates Penetration into the Server Field, x86 and ARM Architectures Feel Great Pressure**

NextSilicon's upcoming RISC-V architecture CPU named "Arbel" is aimed at HPC (high-performance computing) scenarios as a server-class host CPU, tightly coupled with the company's Maverick-2/3 accelerator products to serve supercomputing centers and scientific computing data center loads, but it is still in the test chip stage.

Veteran industry insiders in the semiconductor field generally position "Arbel" as part of a "host + accelerator" supercomputing cluster—designed to build a complete "host + accelerator" stack to challenge the mainstream paradigm of x86 architecture + GPU systems. The RISC-V architecture CPU named "Arbel" specifically targets the server CPU market long dominated by Intel/AMD.

The globally popular open-source instruction set architecture—RISC-V—has rapidly risen in prominence in the chip design field in recent years, gradually moving towards a core position in this domain, forming a tripartite balance of power with the two mainstream architectures ARM under Arm Holdings and x86 under Intel to some extent RISC-V is a completely open instruction set architecture (ISA), which means that any entity can access and use the technology for free. This openness has made RISC-V very popular in academia, startups, and some large technology companies. Since RISC-V has a high overlap with ARM in application scenarios, both focusing on low power consumption and embedded scenarios, ARM is its main competitor. However, in recent years, RISC-V has begun to be used by many developers in the data center field, and it may compete with the x86 architecture in the future, gradually eating into the market share of x86 and ARM architectures in their respective areas of expertise.

From the current public information, compared to Intel and AMD, the CPU products being developed by NextSilicon (code-named "Arbel", RISC-V) prioritize HPC and tightly coupled architectures that can reduce the instruction and data transfer overhead in traditional CPU/GPU architectures. Compared to the mainstream paradigm of x86+GPU, this can significantly improve the energy efficiency and throughput of computing platforms; the open ISA and customization potential based on RISC-V are undoubtedly much greater, making it easier to scale according to the large HPC demands of research labs

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