---
title: "SK Hynix advances AIP process, challenging the bottleneck of NAND manufacturing with over 300 layers"
type: "News"
locale: "en"
url: "https://longbridge.com/en/news/275695337.md"
description: "SK Hynix is developing a new generation of process technology called AIP (All-In-Plug), aimed at achieving high-stacking NAND with over 300 layers while significantly reducing manufacturing costs. AIP technology enhances production efficiency and optimizes cost structure by integrating multiple critical etching processes into a single step. Vice President Lee Sunghoon pointed out in his speech that as the complexity of semiconductor processes increases, traditional technologies have become difficult to support future development. If this technology is successfully introduced into mass production, it will provide an economical manufacturing foundation for higher-layer stacked memory"
datetime: "2026-02-12T03:37:58.000Z"
locales:
  - [zh-CN](https://longbridge.com/zh-CN/news/275695337.md)
  - [en](https://longbridge.com/en/news/275695337.md)
  - [zh-HK](https://longbridge.com/zh-HK/news/275695337.md)
---

> Supported Languages: [简体中文](https://longbridge.com/zh-CN/news/275695337.md) | [繁體中文](https://longbridge.com/zh-HK/news/275695337.md)


# SK Hynix advances AIP process, challenging the bottleneck of NAND manufacturing with over 300 layers

According to reports from South Korean media, SK Hynix is developing a next-generation process technology called AIP (All-In-Plug), aiming to achieve over 300 layers of high-stacked NAND while significantly reducing manufacturing costs.

Compared to existing NAND, which requires multiple critical etching processes, the core concept of AIP is to integrate the related processes into a single step, enhancing production efficiency and optimizing cost structure.

The company's Vice President Lee Sunghoon pointed out in a keynote speech at SEMICON Korea 2026 that as the complexity of semiconductor processes continues to rise, the traditional technological methods used in the past can no longer support future development. Therefore, the company is establishing a technology platform to predict the difficulties of next-generation processes while simultaneously evaluating key precursor technologies for the new generation of DRAM and NAND.

In the NAND field, the number of stacking layers continues to advance beyond 300 layers, causing both manufacturing costs and process difficulties to rise. The AIP technology focuses on the core High Aspect Ratio Contact (HARC) etching process in NAND manufacturing, aiming to reduce the number of repetitive steps by integrating multiple processes, with the goal of lowering production costs and improving capacity efficiency while maintaining process feasibility.

If this technology is successfully introduced into mass production, it is expected to significantly reduce the number of etching steps starting from the next-generation NAND generations like V11, establishing a more economical manufacturing foundation for higher-layer stacked memory.

Lee Sunghoon stated that one of the key factors for the rising costs of high-stacked NAND is the increased number of etching processes. How to integrate multiple steps into a single step is currently an important technical challenge for the company.

-   SK Hynix, shaking up the next-generation NAND landscape... considering the application of 'AIP' technology

（Image source: Technology News）

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