--- title: "TSMC's Advanced Packaging Roadmap Shifts: CoWoS 'Longer Life Cycle', Next-Gen CoPoS 'Earliest Q4 2030'" type: "News" locale: "en" url: "https://longbridge.com/en/news/283085734.md" description: "TSMC's advanced packaging technology roadmap has undergone significant adjustments, with CoPoS mass production delayed to Q4 2030, approximately two years later than originally expected. Consequently, the strategic importance of CoWoS has risen, and its life cycle is significantly extended. This change will impact investment logic across the semiconductor packaging supply chain; while related suppliers face risks, equipment and material suppliers benefiting from CoWoS and SoIC capacity expansion are expected to maintain order visibility. Technical bottlenecks are the primary reason for the CoPoS delay" datetime: "2026-04-17T03:30:01.000Z" locales: - [zh-CN](https://longbridge.com/zh-CN/news/283085734.md) - [en](https://longbridge.com/en/news/283085734.md) - [zh-HK](https://longbridge.com/zh-HK/news/283085734.md) --- # TSMC's Advanced Packaging Roadmap Shifts: CoWoS 'Longer Life Cycle', Next-Gen CoPoS 'Earliest Q4 2030' TSMC's advanced packaging technology roadmap is undergoing significant adjustments. The mass production timeline for CoPoS has been substantially delayed, elevating the strategic position of CoWoS. This shift will profoundly affect the investment logic of the entire semiconductor packaging supply chain. According to a Friday report by DigiTimes, given that the advancement of CoPoS has proven more difficult than anticipated, **TSMC's latest plans indicate that the first batch of CoPoS packaged products will not be produced until at least Q4 2030, delaying the planned 2028 mass production handover by approximately two years.** **Meanwhile, TSMC's CoWoS capacity for the next two years is already fully booked, and the CoWoS life cycle will be significantly extended compared to expectations.** These adjustments mean that supply chain companies betting on early CoPoS mass production face the risk of schedule delays, while equipment and material suppliers continuously benefiting from CoWoS and SoIC capacity expansion are expected to maintain order visibility over a longer period. Additionally, reports suggest that the CoWoP plan, led by NVIDIA and SASE, may also be postponed, further reshaping the market landscape. ## CoPoS Timeline Significantly Delayed; Technical Bottlenecks Are the Main Cause According to DigiTimes citing industry sources, the core technical challenges facing CoPoS stem from two major issues: "uniformity" and "warpage." TSMC had internally believed that CoPoS mass production would not happen quickly. Based on the latest planning milestones, TSMC will begin bringing in equipment for R&D in Q3 2026, with the R&D line construction taking about one year. Equipment orders for the pilot line will only be placed in Q3 2027, with an equipment delivery time of approximately three quarters. In Q2 2028, pilot equipment will enter the P7 facility in Chiayi, followed by another year required for validation and adjustment. It is estimated that after mid-2029, mass production machinery will be finalized and orders placed with the supply chain. After another three quarters for delivery, **equipment will enter the facility in Q1 2030, with the first batch of packaged products expected to be produced no earlier than Q4 2030.** Of particular note, reports indicate that TSMC has extremely high requirements for suppliers participating in the joint development of CoPoS, even requiring some equipment manufacturers to sign restrictive clauses prohibiting them from selling related technologies or machinery to other customers, further raising the entry threshold and development costs for the supply chain. ## CoWoS and SoIC Capacity Expansion Accelerates; NVIDIA Secures Bulk Capacity Against the backdrop of CoPoS delays, the strategic value of CoWoS has become even more prominent. **Not only NVIDIA and AMD, but also ASIC customers have poured in large orders, leaving TSMC's CoWoS capacity for the next two years fully booked.** The AP8 P1 plant in Tainan is expected to reach a monthly capacity of over 40,000 wafers by year-end, while the P2 plant is also under urgent construction. Regarding SoIC, TSMC plans to significantly increase the monthly capacity of its Chiayi plant from nearly 10,000 wafers currently to 50,000 wafers in 2027. NVIDIA will secure the bulk of this capacity, with approximately 10% allocated to optical co-packaging (CPO). This scale of expansion presents clear benefits for hybrid bonding equipment suppliers; market analysts point out that relevant equipment orders are likely to follow suit. Overall, with continued CoWoS expansion and accelerated SoIC volume ramp-up, supply risks for the supply chain over the next few years have decreased significantly compared to before, and the profit visibility for equipment and material manufacturers has correspondingly improved. ## CoWoP Plan Faces Postponement; Supply Chain Landscape Reshaped The CoWoP plan, jointly led by NVIDIA and SASE, may face postponement. The main reasons are that this technology route is more difficult and costly, leading to low participation willingness among SASE and Taiwanese PCB manufacturers. The potential postponement of the CoWoP plan further concentrates market attention on TSMC's own packaging technology routes. With CoPoS mass production still far off and CoWoP progress stalled, CoWoS and SoIC will remain the core pillars of TSMC's advanced packaging for a considerable period. Consequently, the capital expenditure rhythm and order structure of the relevant supply chain will be re-priced accordingly. Risk Disclosure and Disclaimer Markets involve risks; investment requires caution. This article does not constitute personal investment advice and does not take into account the specific investment objectives, financial status, or needs of individual users. Users should consider whether any opinions, views, or conclusions contained herein are appropriate for their specific circumstances. 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