--- title: "Samsung Unveils \"Three-Stage HBM Roadmap\": Toward True 3D zHBM, Stacking DRAM Directly on Compute Chips" type: "News" locale: "en" url: "https://longbridge.com/en/news/296728737.md" description: "At the Hot Chips conference, Samsung disclosed a three-stage HBM roadmap, with the ultimate goal of achieving the zHBM architecture, which stacks DRAM directly onto compute chips to eliminate the interposer. The company claims this solution reduces power consumption by 70%, increases bandwidth by 230%, and saves 100W compared to HBM4E. With current HBM facing physical limits of TSVs and interface bottlenecks, Samsung aims to break through these constraints with its new architecture" datetime: "2026-08-24T02:55:20.000Z" locales: - [zh-CN](https://longbridge.com/zh-CN/news/296728737.md) - [en](https://longbridge.com/en/news/296728737.md) - [zh-HK](https://longbridge.com/zh-HK/news/296728737.md) generator: "portal-rs" --- # Samsung Unveils "Three-Stage HBM Roadmap": Toward True 3D zHBM, Stacking DRAM Directly on Compute Chips Recently, at the Hot Chips technology conference, Sangwook Han from Samsung’s DRAM design team delivered a speech, officially revealing Samsung’s three-stage roadmap for HBM evolution. The endpoint of this roadmap is a new architecture called zHBM, which vertically stacks DRAM directly on top of compute chips such as GPUs and TPUs, completely eliminating the 2.5D interposer. According to a report by wccftech on August 23, Samsung stated that **the zHBM solution claims to achieve a 70% reduction in power consumption, a 230% increase in DRAM bandwidth, and a power saving of 100W per DRAM module, while freeing up an additional 8.3% power headroom for the GPU.** ## What is HBM, and Where Are the Bottlenecks? HBM, or High Bandwidth Memory, is currently one of the most critical storage components in AI training and inference systems. It consists of two types of chips: - C-die (Core Die): Contains DRAM storage cells and can be vertically stacked up to 16 layers high. - B-die (Base Die): Located at the bottom of the entire stack, it handles various DRAM control functions and communicates with compute chips like GPUs via the PHY (Physical Interface Layer). The two are connected via TSV (Through-Silicon Via), a vertical conductive channel that penetrates the chip. According to Wccftech, the current bandwidth of each HBM4 stack exceeds 3TB/s, with HBM4E pushing further into the 4TB/s range. HBM5 doubles the bandwidth based on HBM4, with capacity exceeding 60GB. However, the continuous expansion of bandwidth faces two hard constraints: **the physical limits of TSV count and pitch**, and **the I/O count and speed upper limit of the PHY interface within the Base Die**. Meanwhile, the process node gap between the B-die and the compute chip (xPU SoC) is narrowing with each generation, presenting both a challenge and an entry point for Samsung’s roadmap. ## Stage 1: "Making Room" for Compute Chips The core objective of the first stage of Samsung’s roadmap is to **"reclaim" silicon area from the xPU (compute chip)**. Samsung has applied its D1c and 4nm logic processes to the Base Die (B-die) of HBM4, primarily to reduce power consumption and shrink the effective area. This marks the starting point for the true integration of DRAM with advanced logic processes. Specific measures include: - Replacing the traditional HBM PHY with a D2D (Die-to-Die) interface to shorten channel length, directly improving energy efficiency while freeing up valuable silicon space for the XPU. - Offloading the memory controller from the XPU to the B-die of cHBM, which is expected to free up 5% to 10% of the XPU’s area, corresponding to a 10% to 20% performance improvement. - Introducing an SRAM-based fine-grained repair scheme (Near-MC SRAM-Based Cell Repair), utilizing idle space on the B-die to deploy SRAM repair resources. A side effect of area reduction is heat management issues. To address this, Samsung has launched Heat Path Block (HPB) technology, built on the cHBM4 solution, which can reduce peak temperatures by over 35%, covering 50% of the PHY area. ## Stage 2: The B-die Begins to "Grow" Compute Capabilities The focus of the second stage shifts from "making space" to "adding functionality," which Samsung defines as the **Function Expansion Stage**. **Expanding Memory Capacity.** As the context window of large AI models expands dramatically, the demand for KV Cache (Key-Value Cache, the memory area used to store intermediate states during model inference) is growing exponentially. Samsung plans to integrate memory expansion controllers and PHYs on the idle silicon area of the Base Die, expanding the system's available memory capacity through external solutions such as LPDDR or HBM. **Integrating Processing Elements (PE).** Samsung also proposes integrating some computational Processing Elements on the Base Die, offloading part of the computation originally performed on the xPU to the memory side. This reduces D2D bandwidth requirements, lowers power consumption, and alleviates thermal burden. This form is known as AHBM (Advanced HBM). **Enhancing Reliability and Testability.** The second stage also includes integrating advanced RAS (Reliability, Availability, Serviceability) sensors and real-time telemetry functions on the Base Die, as well as On-Chip Self-Test (ATIP) capabilities, to improve yield and test coverage. ## Stage 3: zHBM—Eliminating the Interposer, DRAM Stacked Directly on Compute Chips The third stage represents the ultimate form of the roadmap: **zHBM**. Current mainstream AI systems adopt a 2.5D packaging architecture, where the GPU and HBM are placed side-by-side on the same interposer, transmitting data via lateral interconnects. The concept behind zHBM is to "stand this structure up"—stacking the DRAM directly on top of the xPU chip to form a true 3D vertical integration. Key features of zHBM described by Samsung include: - Distributed I/O: Minimizing the data transmission distance within the HBM stack. - 3D Structure: Eliminating traditional 2D interfaces to significantly boost system efficiency. - I/O Power Target of Approximately 0.5 pJ/bit: Achieved by removing redundant modules such as SerDes. - Bandwidth increase of over 2.3 times, with a system thermal margin of 100W. Samsung demonstrated a solution with four zHBM stacks superimposed on a single XPU. To achieve these goals, Samsung is developing two key packaging technologies: **WoW (Wafer on Wafer)** and **HCB (Hybrid Cube Bonding)**, to achieve ultra-high I/O density and ultimately build a unified SoC-DRAM co-design ecosystem. ## The Core Logic Behind the Roadmap The core narrative of Samsung’s presentation is repositioning the HBM Base Die from a "passive data transit station" to an "intelligent partner with active computing capabilities." The evolutionary logic of the three stages is clear: first, compress area and free up xPU space through process upgrades (Stage 1); then, utilize the freed-up space to integrate more functions, expanding capacity and computing power (Stage 2); and finally, thoroughly reconstruct the system architecture through 3D vertical integration, breaking through simultaneously in power consumption, bandwidth, and thermal management (Stage 3). In his summary, Samsung stated: "By mastering advanced packaging and unified SoC-DRAM co-design, we will break through the power, area, and capacity bottlenecks constraining AI systems, paving the way for higher efficiency, higher performance, and stronger scalability in the coming years." Risk Warning and Disclaimer The market carries risks; investment requires caution. This article does not constitute personal investment advice, nor does it take into account the specific investment objectives, financial status, or needs of individual users. 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