---
title: "SK Hynix Is Shipping 16-Layer HBM4 for Nvidia Rubin: Where Do Micron And Samsung Stand?"
type: "News"
locale: "en"
url: "https://longbridge.com/en/news/299086512.md"
description: "SK Hynix has begun volume shipping of 16-layer HBM4 for Nvidia's Rubin platform, securing a first-mover advantage. Micron is currently shipping samples of the same configuration, while Samsung has opted not to commercialize it due to limited demand. Despite SK Hynix's lead in memory production, industry analysts identify TSMC's CoWoS advanced packaging as the primary binding constraint, with significant supply gaps and long lead times limiting overall AI accelerator output."
datetime: "2026-09-15T18:23:45.000Z"
locales:
  - [zh-CN](https://longbridge.com/zh-CN/news/299086512.md)
  - [en](https://longbridge.com/en/news/299086512.md)
  - [zh-HK](https://longbridge.com/zh-HK/news/299086512.md)
generator: "portal-rs"
---

# SK Hynix Is Shipping 16-Layer HBM4 for Nvidia Rubin: Where Do Micron And Samsung Stand?

Three companies can manufacture the advanced memory required by Nvidia’s newest artificial intelligence processors.

Only one has reportedly reached volume shipments with the densest configuration.

Silicon Analysts’ latest supply-chain tracker shows **SK hynix Inc.** (NASDAQ:SKHY) shipping a 48-gigabyte, 16-layer HBM4 device for **NVIDIA Corporation** (NASDAQ:NVDA)’s Vera Rubin platform.

That is one step beyond the company’s own last public statement.

The AI memory race between **SK Hynix**, **Samsung Electronics Co. Ltd** (OTC:SSNLF) and **Micron Technology Inc**. (NASDAQ:MU) has therefore moved beyond HBM4 qualification. 

The new battleground is how quickly each supplier can manufacture increasingly dense memory stacks at commercial scale.

## Why 16-Layer HBM4 Matters

HBM stands for high-bandwidth memory. It is DRAM stacked vertically next to a processor so that an AI accelerator can be fed data fast enough to keep its compute cores working.

Each added layer raises capacity per stack. The 16-layer part holds 48 gigabytes against 36 gigabytes for the 12-layer version, a 33% increase in capacity per memory placement.

Adding four layers inside the same ceiling requires thinner dies and tighter gaps between them, which is why the 16-layer part has been the hardest step in the generation.

Silicon Analysts said SK Hynix began mass-producing its 48-gigabyte, 16-layer HBM4 device during the third quarter.

Placing more memory closer to the processor reduces data-transfer delays. It also allows AI systems to run larger models without using additional memory packages.

Silicon Analysts called SK Hynix’s move "the sharpest supply-chain signal this week."

The shipment also demonstrates something competitors cannot replicate overnight: manufacturing yield.

Stacking 16 memory dies increases production complexity. Each layer must communicate reliably while remaining within strict power, heat and physical-size limits.

Silicon Analysts said the milestone "cements first-mover advantage" for SK Hynix.

 **Read Also: Anthropic's AI Warning Is 'Noise' in a 'Secular Bull Market:' Bank of America Says** 

## **Where Micron And Samsung Stand**

Micron has been in high-volume production of 12-layer HBM4 for Nvidia Rubin since March and has shipped 48-gigabyte 16-layer samples to customers. 

It has not announced volume production of the taller part.

Samsung Electronics Co. began mass-producing HBM4 in February. 

Its HBM3E 12-layer product cleared Nvidia qualification during the week ended Sept. 14, and its HBM4 12-layer stack is in the final qualification phase, according to Silicon Analysts.

Samsung told investors on its fourth-quarter 2025 call that customer demand for a 16-layer product is limited and that commercializing it is unnecessary, while stating it holds the technology to do so if requirements change.

| Company                     | 12-Layer HBM4          | 16-Layer HBM4             |
| --------------------------- | ---------------------- | ------------------------- |
| **SK Hynix Inc.**           | Mass production        | Volume shipping (tracker) |
| **Micron Technology Inc.**  | High-volume production | Samples shipped           |
| **Samsung Electronics Co.** | Final qualification    | Not commercialized        |

*Source: company statements, Silicon Analysts (Sept. 14, 2026)*

## **Packaging Is The Binding Constraint**

Memory is no longer the slowest step in building an AI system. 

Silicon Analysts estimates that lead times for **Taiwan Semiconductor Manufacturing Co. Ltd.** (NYSE:TSM)’s CoWoS advanced packaging have stretched to 52–78 weeks.

CoWoS, short for Chip-on-Wafer-on-Substrate, is TSMC’s advanced packaging technology for connecting Nvidia’s processors with their high-bandwidth memory inside one finished AI chip package.

Without sufficient packaging capacity, additional processors and memory cannot become finished AI accelerators.

Silicon Analysts said "packaging, not silicon, remains the binding constraint."

No merchant alternative exists to CoWoS.

Capacity is rising toward 120,000 to 130,000 wafers per month by the end of 2026 and 141,000 to 170,000 in 2027, but TrendForce still estimates a supply gap near 20% this year.

Micron reports fiscal fourth-quarter results on Sept. 30, the next verifiable read on HBM pricing and volumes.

 **Read Also: Marvell Stock Is Up 180% This Year: BofA Says the Real AI Opportunity Is 5 Times Bigger** 

*Image: Shutterstock*

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---
> **Disclaimer: This article is for reference only and does not constitute any investment advice.**