Direct Response to CXMT's 4F2 Breakthrough: Micron CTO Says 3D DRAM Is "More Scalable and Cost-Effective in the Long Run"

Recently, the global memory chip market has seen a new round of valuation volatility and debate over technological roadmaps. In the capital markets, the Philadelphia Semiconductor Index and the memory sector have experienced significant pullbacks; on the industrial front, CXMT's breakthrough progress in 4F² DRAM architecture has sparked widespread industry discussion.

On October 21, Scott DeBoer, President and Chief Technology and Product Officer of Micron Tech, hosted a technology and product webinar. One of the core topics was addressing investor concerns triggered by CXMT's earlier disclosure of its 4F² architecture plans.

Scott DeBoer stated bluntly, "Although we conducted long-term evaluations and prototype verification of 4F² internally, Micron will adhere to the existing 6F² route and ultimately move directly to 3D DRAM. Micron believes that from a long-term evolutionary perspective, 3D DRAM is a more certain choice in terms of 'scalability and cost-effectiveness.'"

He further explained that the key factor determining DRAM bit density and cost scalability is capacitor pitch. The vertical channel access transistor (VCAT) in the 4F² architecture lacks a viable scaling path beyond pitch reduction.

According to reports from Zhuifeng Trading Desk, a subsequent research report by UBS analyst Timothy Arcuri's team pointed out that if Micron's judgment is correct and the industry ultimately shifts toward 3D DRAM, suppliers of deposition and etching equipment are expected to benefit.

As previously mentioned by Wall Street News, Cao Kanyu, President of CXMT, disclosed on October 10 that the company plans to launch a new generation of DDR5 RDIMMs based on the 4F² architecture by year-end. Compared to the mainstream 6F² architecture, this could reduce chip area by approximately 30%, allowing more chips to be cut from a single wafer.

Micron's Core Argument: 4F² Is Not the Path to the Future

The reason CXMT's 4F² technology has attracted significant industry attention is that it directly addresses the most fundamental commercial pain point of DRAM chips— bit density per wafer and cost.

In traditional DRAM design, the industry mainstream largely adopts the 6F² architecture. If a successful transition to 4F² is achieved, it could theoretically reduce cell area by more than 30% at the same process node, significantly increasing the number of effective dies produced per wafer.

After tracking Micron's technical communications, UBS pointed out that Micron conveyed its judgment on the mass production bottlenecks of 4F² to the market:

First, the bottleneck lies in capacitors, not transistors. Micron believes that the ultimate bottleneck in DRAM scaling is capacitor pitch, not merely the transistor cell structure. If capacitor pitch cannot be compressed simultaneously, simply changing to a 4F² structure will not linearly translate into sustained cost advantages.

Second, the scaling ceiling of VCAT. 4F² typically requires the introduction of Vertical Channel Access Transistors (VCAT). Micron pointed out that VCAT lacks a sustainable subsequent evolution path beyond continuing to compress pitch, and it imposes extremely high manufacturing complexity on processes such as ALD (Atomic Layer Deposition) and selective epitaxy. Mass production costs may erode the benefits gained from area reduction.

According to a post-conference summary by Deutsche Bank analyst Melissa Weathers, Micron not only clearly stated that it does not plan to transition to the 4F² architecture but also emphasized that the company had conducted decades of internal evaluation and developed prototypes for the 4F² solution. However, the final conclusion was: "Before the industry moves toward 3D DRAM, 6F² remains the more attractive path."

Major Manufacturers Show Distinctly Different Technical Considerations

UBS analysis pointed out that Micron's statement effectively indicates it is pursuing two parallel technical paths, similar to its dual preparation regarding the adoption of EUV at the 1-beta node. The company believes that 3D DRAM will eventually converge with its roadmap and views it as a "more scalable and cost-effective" long-term solution.

However, Micron's logic does not represent the consensus of the entire industry.

Concurrent research by UBS showed that, in addition to CXMT's full-scale breakthrough in this direction, industry leader Samsung is also rumored to be considering introducing the 4F² architecture at its future 0a nm node to alleviate process pressure caused by the high aspect ratio of capacitors.

Samsung plans to complete mass production of 6F² at the 1d nm node in 2027 and then promote the introduction of 4F² at the 0a nm node by the end of 2028.

Micron's Technology Narrative

In addition to directly responding to doubts about 4F², Micron also emphasized its comprehensive technology layout during this webinar.

Expansion of AI Memory Map: Micron emphasized that AI's demand for memory is not limited to training HBM alone but also includes LPDDR6, DDR6, SOCAMM, and 1TB large-capacity RDIMMs required for inference, edge AI, and autonomous driving.

Advanced Packaging and Logic Integration: Micron views Hybrid Bonding as the core moat for future 16-High and higher-specification HBM and is actively promoting cooperation with foundries to develop vHBM (vertical stacking of memory on top of computing cores). Micron attempts to prove that competition in storage during the AI era has shifted from "single-bit cost control" to "system-level synergy of memory, packaging, and logic architecture."

Reshaping NAND Value: Micron also showcased its Gen11 NAND roadmap with over 400 layers, emphasizing the demand for high-performance storage with high IOPS and high bandwidth in the AI era, striving to build a comprehensive barrier through the synergy of DRAM and NAND.

The Real Impact of CXMT's 4F²: Market Reaction May Be Overinterpreted

Regarding the market concerns triggered by CXMT's 4F² announcement, several institutions have previously made relatively prudent assessments.

Nomura Securities believes that neither 4F² nor 3D DRAM will have a "substantial impact" within the outlook period before 2028, and CXMT's mass production of 4F² is not expected to be realized until 2027–2028. CITIC Securities also warned that 4F² is currently in an early verification stage, with yield, output, and customer certification yet to be observed, limiting its impact on the mid-term memory industry landscape.

In terms of CXMT's own industrial position, its HBM business is still in its infancy, making it difficult to share the high-premium dividends of this niche market driven by AI computing power in the short term. Against the backdrop of a significantly narrowing slope in general DRAM price increases, this structural characteristic leaves it with relatively little room for hedging.

Tracking data from TrendForce shows that the quarter-on-quarter increase in contract prices for general DRAM has narrowed sequentially from 93%–98% in Q1 2026 to 13%–18% in Q3, and is expected to further drop to 10%–15% in Q4.