Nvidia’s next generation chip platform, Feynman is ahead of schedule, will use TSMC’s A16 process, and CPO (co-packaged optics), DigiTimes reports, with TSMC full speed ahead to meet 2028 mass production.
-Nvidia is rapidly shifting its supply chain to put Feynman out in the 2nd half of 2028-Feynman uses 3D chiplets, SoIC packaging and CPO. (Silicon-on-Integrated-Chips).-Total rack bandwidth for Feynman to hit 1,000 TB/s versus 260 TB/s for Rubin and 520 TB/s for Rubin Ultra, making CPO vital.-TSMC construction at advanced packaging plants AP7 in Chiayi and AP8 in Tainan are ahead of schedule, and accelerating-SoIC, CoWoS-L and CoPoS are all being pulled forward-SoIC capacity seen at 50,000 wafers-per-month (wpm) by end-2027, vs end-2026's 20,000wpm $NVIDIA(NVDA.US) $Taiwan Semiconductor(TSM.US) #semiconductorsSource: Dan Nystedt
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