Co-packaged optics (CPO) has officially entered the mass-production deployment stage, but the critical testing processes responsible for safeguarding yield continue to face different challenges across Insertion 1 through Insertion 4.

Supply chain sources noted that conventional semiconductor electrical testing is typically measured in seconds. By comparison, Insertion 1 testing of photonic integrated circuits (PICs) can take more than 10 minutes for a single die. With a testing system costing millions of US dollars, the resulting testing costs remain too high to deliver sufficient commercial value for volume production.

A similar challenge exists at Insertion 2, which tests electronic-photonic integrated circuits (EPICs). Because the electronic IC (EIC) and PIC are integrated through hybrid bonding, creating an architecture with electrical circuitry above and photonics below, testing is constrained by limited industry experience in simultaneously testing both the electrical and optical sides. Wafer warpage presents another challenge, with testing times in some cases extending to as long as 30 minutes.

Source: Chips & Wafers