--- title: "MicroCloud Hologram's FPGA quantum computing simulation framework based on series-parallel architecture — An efficient hardware simulation platform for future quantum computing" type: "News" locale: "en" url: "https://longbridge.com/en/news/287706060.md" description: "Weiyun Hologram has launched an FPGA quantum computing simulation framework based on a series-parallel architecture, aimed at addressing the current limitations of quantum computers and supporting large-scale quantum algorithm verification. This framework achieves a linear decrease in resource utilization through innovative data path design, demonstrating the speed and parallel advantages of hardware simulation. Verification has been completed on core algorithms such as quantum Fourier transform and Grover's search, providing a scalable path for simulating future circuits with hundreds to thousands of quantum bits" datetime: "2026-05-27T02:44:17.000Z" locales: - [zh-CN](https://longbridge.com/zh-CN/news/287706060.md) - [en](https://longbridge.com/en/news/287706060.md) - [zh-HK](https://longbridge.com/zh-HK/news/287706060.md) generator: "portal-rs" --- # MicroCloud Hologram's FPGA quantum computing simulation framework based on series-parallel architecture — An efficient hardware simulation platform for future quantum computing With the rapid development of global quantum computing technology, how to conduct large-scale quantum algorithm verification in the context of real quantum computers not being fully mature and the limited scale of qubits has become a key issue of common concern in both academia and industry. To fill the technical gap where software quantum simulators are limited in performance and cannot support large-scale quantum circuit verification, MicroCloud Hologram (NASDAQ: HOLO) has launched a new FPGA quantum computing simulation framework based on a serial-parallel architecture. This framework employs an innovative hardware-level data path design, achieving a linear decrease in resource utilization by redefining the execution method of quantum gate operations. This framework not only demonstrates the inherent advantages of hardware simulating quantum systems in terms of speed and parallelism but also marks a critical step forward for MicroCloud Hologram in the direction of quantum computing hardware acceleration. The technology has been validated on core quantum algorithms such as Quantum Fourier Transform (QFT) and Grover Search, providing a scalable path for simulating quantum circuits at the level of hundreds to thousands of qubits in the future. The rapid evolution of quantum algorithms has created an urgent need for researchers and engineering teams for tools that can verify, debug, and test large-scale quantum circuits. However, today's real quantum computers are still subject to various limitations, including insufficient qubit numbers, error correction mechanisms still under development, and significant system noise interference. These limitations mean that many complex quantum algorithms cannot be run directly on quantum machines. Traditional software quantum simulators, while flexible, have obvious performance bottlenecks. Quantum states can be mathematically represented as exponentially scaled vectors, and when the number of qubits exceeds 40, even large servers or GPU clusters struggle to meet the exponential memory and computational demands. Hardware-level simulation, especially FPGA (Field-Programmable Gate Array)-based simulation technology, has become a future direction of interest in both academia and industry due to its high parallelization, customizable circuits, low latency, and relatively low energy consumption. Previous FPGA quantum simulation architectures mostly adopted a pipelined design, which, while improving throughput, also brought engineering challenges such as increased resource consumption, higher circuit complexity, and limited scalability. How to compress resource usage while ensuring high performance has become the core difficulty in designing FPGA quantum computing simulation frameworks. The technological achievements released by MicroCloud Hologram successfully address the high resource consumption issue of quantum gate operations in hardware mapping through an advanced hardware architecture design that combines serial and parallel processing, allowing quantum algorithms to be integrated into FPGA in a more efficient manner. Traditional pipelined FPGA implementations typically expand quantum gate operations into a large number of parallel logics, which can lead to exponential resource overhead when handling multi-qubit gates (such as controlled-NOT, controlled-phase, and continuous cascading phase gates in QFT). The new architecture adopts a combination of serial and parallel modes, decomposing and scheduling quantum gate operations so that the execution of quantum gates can be reused in the time dimension rather than being hard-expanded in the spatial dimension. At the logical level, MicroCloud Hologram (NASDAQ: HOLO) implements this architecture by processing quantum state vectors as data streams in a serial manner within the hardware, allowing each qubit to share a large amount of resources when receiving gate operations through strict control of the data path For key steps that need to be executed in parallel, acceleration is achieved through appropriately designed parallel modules, thus finding a balance between performance and resource consumption. The core idea of this hybrid architecture is: parallel processing is used for critical data throughput, while serial processing is used for gate-level reuse, achieving a comprehensive linear saving of resources. This represents an important technological breakthrough in hardware quantum simulation architecture. Implementing quantum algorithm simulation in FPGA relies heavily on the design of the datapath. The MicroCloud Hologram framework optimizes the entire link from data flow control, register layout to fixed-point quantization strategy, allowing resource usage to increase approximately linearly with the number of qubits, rather than exponentially. Firstly, by optimizing the quantum state loading method, the system supports segment-wise reading and processing of quantum state amplitudes without needing to store all amplitudes internally in the FPGA. This local state caching + streaming read approach effectively reduces the usage ratio of BRAM and LUT. Secondly, the quantum gate operation module adopts a reconfigurable operator design, allowing multiple quantum gates to be executed in turn on the same hardware resource. This processing method, similar to out-of-order execution in superscalar CPUs, is used for quantum algorithm simulation on FPGA for the first time, greatly reducing the demand for logical resources. More critically, this architecture introduces an operator time-slice allocation mechanism, scheduling quantum gates to execute in different cycles, allowing the same logical unit to serve different qubits. This approach prevents the hardware consumption of multi-qubit gates from increasing exponentially. Experimental validation on QFT and Grover algorithms shows that this architecture exhibits a linear decrease in resource occupancy compared to traditional pipelined solutions, which has been difficult to achieve in previous literature and engineering implementations. Quantum Fourier Transform (QFT) is central to many quantum algorithms, including Shor's factoring algorithm, quantum phase estimation, and many quantum machine learning toolchains. In classical systems, QFT requires handling a large number of controlled phase shift gates and swap operations, resulting in significant hardware overhead. The MicroCloud Hologram framework implements the following key technologies in QFT simulation: - A streaming read mechanism for quantum state amplitudes, allowing transformations to gradually act on each segment of data without needing complete storage. - Controlled phase shift gates utilize a configurable rotation module based on angle indexing, enabling the reuse of lookup table units within the FPGA, thereby reducing LUT consumption. - Swap operations between adjacent qubits are handled through hardware-level multiplexers, not relying on a large number of fixed connections, thus improving circuit scalability. - With the overall hardware scale fixed, the QFT circuit scale can be expanded to its limits, constrained only by the capacity of external storage, rather than the internal logic resources of the FPGA Experimental results show that this implementation can achieve QFT behavior consistent with software simulation while consuming lower power and occupying fewer resources, providing a hardware foundation for future large-scale quantum algorithm verification. To further validate the universality of the framework, the MicroCloud Hologram R&D team used Grover's search as a second verification case. As a representative algorithm for quantum accelerated search, the core of Grover's algorithm includes Oracle construction, Hadamard matrix operations, and diffusion transformations. The design features the following characteristics: - The Oracle module is implemented through reconfigurable mapping of Boolean functions, allowing different problem sizes and search modes to run on the same hardware structure. - The diffusion transformation introduces complex arithmetic optimization, enabling amplitude inversion to be completed through a single composite operation, reducing cycle overhead. - The Hadamard operation adopts a folded structure, allowing multiple Hadamard operations to share a single logic module, achieving efficient hardware reuse through time division multiplexing. Experiments show that this framework achieves an order of magnitude speedup when processing Grover's algorithm compared to traditional software simulators while maintaining low hardware occupancy, making FPGA simulation an important engineering tool for future quantum algorithm debugging. MicroCloud Hologram (NASDAQ: HOLO) has developed not just an FPGA quantum algorithm simulator, but a complete baseline framework. Future research based on hardware quantum simulation can be expanded upon this foundation. The framework provides a complete hardware template, including quantum state read/write modules, quantum gate execution modules, complex arithmetic units, data path managers, and high-level controllers, enabling rapid construction of new algorithm simulation modules. The FPGA quantum computing simulation framework based on a serial-parallel architecture marks a significant breakthrough in quantum computing hardware simulation capabilities. Through innovative serial-parallel design, data path optimization, resource reuse strategies, and successful case validation, this framework provides an engineered, scalable, and low-cost solution for future large-scale quantum algorithm verification. This is not only a technological innovation but also an important infrastructure construction for the future development of quantum computing. It is believed that this framework will become one of the quantum algorithm simulation standards used jointly by academia and industry, accelerating the true engineering implementation and large-scale application of quantum computing ### Related Stocks - [HOLO.US](https://longbridge.com/en/quote/HOLO.US.md) - [SMH.US](https://longbridge.com/en/quote/SMH.US.md) - [SOXL.US](https://longbridge.com/en/quote/SOXL.US.md) - [SOXX.US](https://longbridge.com/en/quote/SOXX.US.md) - [FTXL.US](https://longbridge.com/en/quote/FTXL.US.md) - [XSD.US](https://longbridge.com/en/quote/XSD.US.md) - [PSI.US](https://longbridge.com/en/quote/PSI.US.md) - [HOLOW.US](https://longbridge.com/en/quote/HOLOW.US.md) ## Related News & Research - [Tech Has Ignored Rates For Months. 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