---
title: "Taiwan Semiconductor develops AI chip packaging technology to compete with Intel"
type: "News"
locale: "en"
url: "https://longbridge.com/en/news/294374649.md"
description: "Taiwan Semiconductor is developing advanced chip packaging solutions that benchmark Intel's EMIB technology, aiming to alleviate the capacity bottleneck caused by the surge in demand for AI chips. This technology is jointly developed by Taiwan Semiconductor and Unimicron Technology Corporation and has been communicated to customers. Due to the tight existing advanced packaging capacity at Taiwan Semiconductor, Intel is seizing this opportunity to attract customers, while companies like NVIDIA are also evaluating the adoption of Intel's technology to diversify risks and enhance AI chip performance"
datetime: "2026-07-30T13:23:15.000Z"
locales:
  - [zh-CN](https://longbridge.com/zh-CN/news/294374649.md)
  - [en](https://longbridge.com/en/news/294374649.md)
  - [zh-HK](https://longbridge.com/zh-HK/news/294374649.md)
---

# Taiwan Semiconductor develops AI chip packaging technology to compete with Intel

Two individuals familiar with the project revealed that Taiwan Semiconductor Manufacturing Company (TSMC) is developing an advanced chip packaging technology that is comparable to Intel's existing solutions.

Chip packaging is the final step in chip manufacturing. This process assembles multiple independent silicon chips into a whole, completing the interconnection of circuits, allowing various chips to operate in coordination, and achieving connectivity between the chip and other hardware of the entire machine. Packaging was once considered a routine step in semiconductor manufacturing, but with the explosive demand for AI chips, chip design companies need to integrate more processors with high-bandwidth memory into larger and more complex packaging structures. Packaging has now become one of the most prominent capacity bottlenecks in the entire industry.

Intel has developed its own Embedded Multi-die Interconnect Bridge (EMIB) technology. This technology builds high-speed communication links between processors and memory using micro-silicon chips. Potential customers like NVIDIA are highly interested in this technology: EMIB can support larger-scale multi-chip architectures, helping to create more powerful AI chips while allowing chip manufacturers to diversify supplier risks. Media reports indicate that NVIDIA is evaluating the use of EMIB technology to develop a next-generation processor that integrates four graphics card chips within the same package.

Insiders stated that TSMC's internal engineers refer to their advanced packaging project as "EMIB-like technology," and the company has communicated this plan with some customers. TSMC is jointly developing this technology with Unimicron Technology Corporation, which specializes in packaging substrates. The substrate serves as the carrying base for chip packaging and also undertakes the signal transmission function between the chip and other hardware in the server.

TSMC declined to comment; Unimicron did not respond to media inquiries.

TSMC President Wei Zhejia admitted during this month's earnings call that the company's existing advanced packaging capacity is extremely tight, which has limited customers' business expansion. The capacity shortage has created a rare opportunity for Intel to compete for long-term customers that heavily rely on TSMC.

Even if customers initially transfer their packaging business to Intel, such collaborations can help the American company demonstrate its technology and deepen customer ties, ultimately securing more wafer foundry orders.

The shift in industry dynamics is highly symbolic for Intel. For years, Intel has been trying to win back high-end customers with the highest process requirements. This American chip company once led the global advanced chip manufacturing race but has faced multiple production delays, allowing TSMC to overtake it, with many leading chip design companies increasingly entrusting their high-end flagship products to TSMC for foundry services.

Currently, top chips from companies like NVIDIA are all manufactured by TSMC. Meanwhile, Intel is fully laying out its wafer foundry business, striving to compete on the same stage as TSMC. In the process of reshaping its reputation in process foundry, advanced packaging has become another path for Intel to attract customers. Reports indicate that after months of validating Intel's EMIB technology, Google has placed an order for Intel to complete the packaging of over 3 million self-developed AI processors by 2028 For TSMC, this EMIB-like technology is a countermeasure to prevent Intel's packaging advantages from continuing to expand. According to informed sources, this research and development is still in the early stages, and the timeline for commercial mass production is not yet determined. However, this move is sufficient to demonstrate that the AI boom is forcing the global wafer leader to expand its packaging technology matrix—customers need more capacity and more next-generation processor integration packaging solutions.

TSMC's Chip-on-Wafer-on-Substrate (CoWoS) packaging technology is the mainstream packaging solution for AI chips from manufacturers like NVIDIA and Google. AI processors require continuous retrieval of massive amounts of data from memory, necessitating a close arrangement between processors and memory, relying on high-speed links for communication.

TSMC's CoWoS builds high-speed interconnections relying on an intermediary layer beneath the processor and memory. In contrast, Intel's EMIB approach is entirely different: it embeds micro-silicon bridges within the packaging substrate only at points requiring high-speed communication, rather than arranging all components on the same layer. This architecture is more suited to the increasing size and complexity of current chip designs.

This also means that the substrate is the core element of TSMC's EMIB-like packaging research and development. Unimicron Technology Corporation can assist TSMC in the design and manufacturing of the substrate, which is used to support the silicon bridge structure while connecting various chip components above

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