--- title: "SK Hynix Publishes CPO Roadmap in Prestigious Journal: Extending Optical Connectivity Beyond Compute to Memory Interfaces" type: "News" locale: "en" url: "https://longbridge.com/en/news/296425974.md" description: "SK Hynix, in collaboration with institutions such as the University of Virginia, published a paper on the Co-Packaged Optics (CPO) technology roadmap in Nature Electronics. The article highlights that while computing power triples every two years, interconnect bandwidth only increases by 1.4 times, making the \"bandwidth wall\" a core bottleneck for AI scaling. CPO is identified as the key to breaking through this barrier, with a broader vision of extending CPO to memory interfaces, allowing multiple AI accelerators to share a single memory pool and improving memory utilization efficiency" datetime: "2026-08-20T02:36:12.000Z" locales: - [zh-CN](https://longbridge.com/zh-CN/news/296425974.md) - [en](https://longbridge.com/en/news/296425974.md) - [zh-HK](https://longbridge.com/zh-HK/news/296425974.md) --- # SK Hynix Publishes CPO Roadmap in Prestigious Journal: Extending Optical Connectivity Beyond Compute to Memory Interfaces On August 20, researchers from SK Hynix and the University of Virginia jointly published a paper in the top scientific journal _Nature Electronics_, systematically outlining the development roadmap for Co-Packaged Optics (CPO) technology in high-performance computing and AI. This marks the first time SK Hynix has publicly disclosed its technical blueprint for AI interconnect architecture in a journal of this caliber. The paper argues that while High Bandwidth Memory (HBM) has resolved memory bottlenecks within chips, data transmission between racks has become a new constraint as AI clusters scale to thousands of GPUs—known as the "bandwidth wall." CPO is positioned as the critical path to overcome this bottleneck. The long-term vision proposed in the paper is to extend optical interconnects further to memory interfaces. In existing solutions, **optical interconnects primarily address data transmission between processors and between racks. However, the "optics-centric" architecture proposed in the paper directly connects the processor resource pool (XPU pool) with the memory resource pool (memory pool) via a photonic interposer. This enables multiple AI accelerators to share large-capacity memory, breaking through the physical limitations of current packaging.** The corresponding authors of the paper are Seunghoon Hong, Head of the AI Infrastructure Team at SK Hynix, and Kyusang Lee, Professor in the Department of Electrical and Computer Engineering at the University of Virginia. Participating institutions also include the University of Illinois Urbana-Champaign (UIUC), Nanyang Technological University (NTU), the Massachusetts Institute of Technology (MIT), and Yonsei University. In early trading today, SK Hynix surged more than 11% driven by news of the CPO paper and its share buyback plan. Domestic CPO concept stocks fluctuated upward, with Taichenguang rising over 12%, Zhongjing Electronics hitting the limit up earlier, and Tianzhun Technology, Shijia Photons, Dekeli, and Lianite Technology all gaining more than 6%. ## The Bandwidth Wall: Stronger Compute, More Pronounced Bottlenecks AI model training is no longer confined to a single chip or server but operates across large-scale networks composed of racks and pods. In this architecture, overall system performance depends not only on the connection efficiency between processors and memory but also heavily on the speed of data transmission between racks. Data shows that computing power grows approximately threefold every two years, while interconnect bandwidth increases by only about 1.4 times during the same period. This divergence is the source of the "bandwidth wall." Traditional copper electrical interconnects remain cost-effective for short distances, but as transmission speeds increase and distances lengthen, signal loss and power consumption rise sharply, requiring increasingly complex compensation circuits and resulting in higher latency. Kyusang Lee pointed out directly in the paper: "Even if compute chips become more powerful, overall system performance cannot improve if data transmission between chips cannot keep pace. Replacing copper interconnects, which have inherent physical limitations, with optical interconnects is the most promising path to achieve future scalability." ## CPO: Integrating Optical Engines into Processor Packaging The core idea of CPO is to integrate optical transceivers (TRx) into the same package as the processor, allowing chips to exchange data using optical signals rather than long-distance electrical signals. Seunghoon Hong described it as follows: "CPO fundamentally changes how data flows in AI systems, eliminating one of the biggest obstacles to scaling compute power." Specifically, CPO compresses the distance that high-speed electrical signals need to travel to the minimum, with the remaining path handled by optical links. This retains the efficiency of electrical interconnects within the package while leveraging the low-loss characteristics of light for high-speed transmission across chips, racks, and pods, along with stronger resistance to electromagnetic interference. The paper sets clear technical targets for next-generation AI infrastructure: bandwidth per node exceeding 100 Tb/s, energy consumption below 1 pJ/bit, and inter-chip latency under 10 nanoseconds. The paper also outlines the evolution path of CPO from 2D and 2.5D interposer configurations to 3D heterogeneous stacking, listing key technical challenges that must be overcome for commercial deployment. ## A Longer-Term Goal: Extending Optics to Memory Interfaces The long-term vision proposed in the paper is to extend optical interconnects further to memory interfaces—an architectural concept that goes beyond current CPO discussions. In existing solutions, optical interconnects primarily address data transmission between processors and between racks. However, **the "optics-centric" architecture proposed in the paper directly connects the processor resource pool (XPU pool) with the memory resource pool (memory pool) via a photonic interposer.** The practical significance of this architecture lies in the fact that **multiple AI accelerators can share a large-capacity memory pool, rather than each accelerator having its own independent memory. This not only improves memory utilization efficiency but also provides AI infrastructure with more flexible scalability as model sizes continue to grow.** Kyusang Lee stated, "Extending optical interconnects to memory interfaces will break through the physical limitations around compute chips, removing constraints on memory capacity and the number of electrical connections." Hong added, "The greatest advantage is that by improving data movement efficiency, AI systems can scale more flexibly. This ultimately provides customers with the foundation for more efficient operation of AI infrastructure." ## From HBM Supplier to System Architecture Participant HBM solved the memory bandwidth problem within AI accelerator packages and has been SK Hynix's core competitiveness in recent years. The release of the CPO roadmap signifies that the company is extending its technological layout from single components to system-level architecture. Hong clearly expressed this shift in an interview: **"Memory companies are evolving from providers of single components to partners helping enhance the competitiveness of customers' entire systems through technologies like CPO."** Kyusang Lee also pointed out that collaboration between academia and industry is indispensable in this process: "Academia excels at pushing performance boundaries, while industry understands the practical requirements of large-scale deployment—including manufacturing yield, cost, thermal management, and supply chain. Combining these two perspectives is essential to developing a feasible roadmap." He also acknowledged that the path to commercialization still faces significant challenges: "From integrating low-power photonics devices to developing consistent protocols and improving system reliability, the challenges remain substantial. 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