AI boom, profit surge fuel China’s ambitious chip assembly buildout

China’s leading semiconductor packaging and testing companies have launched a multibillion-dollar capacity expansion drive, as they ride a surge in artificial intelligence demand, stellar first-half profit growth, and Beijing’s urgent push for tech self-sufficiency. In the first half of the year, China’s three leading outsourced chip packaging companies – Jiangsu Changjiang Electronics Technology (JCET), Tongfu Microelectronics and Huatian Technology – announced capacity expansion investments exceeding a combined 15 billion yuan (US$2.2 billion). Packaging and testing are the final steps in chip manufacturing. The fresh capital is aimed at scaling the firms’ high-end advanced packaging for AI accelerators, after the companies reported robust earnings growth in the first six months of 2026. JCET, China’s largest packaging and testing firm, saw its net profit surge 79.4 per cent year on year to 845 million yuan, while revenue hit a record 19.5 billion yuan on strong computing electronics sales, according to its earnings report last week. In June, the firm unveiled a 7.8 billion yuan plan for a sprawling new advanced packaging and testing facility for high-end AI chips in Shanghai’s Lingang area, with phase one scheduled for completion in the second half of 2028. Meanwhile, Tongfu Microelectronics – slated to release its latest earnings results on Friday – has forecast a first-half profit surge of up to 337 per cent year on year, driven partly by its strategic partnership with US semiconductor firm Advanced Micro Devices’ next-generation processors. The Chinese company recently received regulatory approval for a 4.2 billion yuan private share placement, and plans to allocate 888 million yuan to add 849,600 wafers of annual memory chip capacity. Huatian Technology, based in northwest China’s Gansu province, reported last week a 259 per cent profit jump in first-half profit to 813 million yuan. It announced a 3 billion yuan investment in May for a Nanjing facility designed to produce 430 million memory chips annually. The capacity race reflects how advanced packaging – including 2.5D, 3D stacking and chiplet architectures – has shifted to centre stage as physical limits slow traditional silicon scaling under Moore’s Law. China’s domestic champions are also receiving a further boost from Beijing’s drive for technological self-reliance. “The value of advanced packaging can reach tens or even hundreds of times that of traditional packaging, driving a revaluation across the industry chain,” analysts at mainland brokerage China Securities wrote in a recent research note. They highlighted that in Nvidia’s B200 AI processor, the combined cost of CoWoS (Chip-on-Wafer-on-Substrate) packaging and testing now rivalled advanced node wafer manufacturing itself. With Taiwan Semiconductor Manufacturing Company’s CoWoS capacity tightly constrained, outsourced chip assembly and test providers are benefiting from strong pricing power. The momentum extends to smaller domestic players. SJ Semiconductor raised 5 billion yuan via an initial public offering on Shanghai’s Star Market to fund 3D multi-chip integration projects, while Forehope Electronic announced in June a 10.3 billion yuan investment for its phase-three facility in eastern China’s Zhejiang province. Globally, major players in chip packaging and testing have also set aside massive capital to solidify their positions amid the rapid expansion wave. ASE Technology Holding, the Taiwan-based industry leader, in July raised its 2026 capital expenditure budget to US$10.5 billion – up from the US$8.5 billion target set in April.