By Dave Lammers, Contributing Writer

From the 2026 Symposium on VLSI Technology and Circuits in Honolulu — a record-low 23% acceptance rate on a record number of submissions — Dave Lammers leads with OpenAI hardware chief Richard Ho’s keynote call to stop optimizing transistors in isolation. Progress on Perf/Watt and Perf/TCO, Ho argued, now depends on co-optimizing compute, memory, and interconnect as a system, not as separate scaling problems — a theme echoed across the conference’s technical sessions.

On the device roadmap itself, IBM’s Dechao Guo mapped transistor innovation out to 2040: after 12 years of FinFETs, the industry is mid-transition to gate-all-around (GAA), with stacked CFETs bonding two optimized wafers together expected in the post-1nm, 2-Angstrom era. Interconnects will need cobalt or ruthenium liners and larger copper grains beyond 20nm pitch, and High-NA lithography becomes necessary at 1.4nm and mandatory at 1nm. TSMC’s L.C. Lu detailed CoWoS packaging scaling to 14x today’s reticle size and a 34x jump in HBM bandwidth between HBM3 and HBM5, while Micron’s Nirmal Ramaswamy targeted sub-50nm wafer-to-wafer overlay for DRAM stacking.

A recurring subplot was memory supply: SK hynix’s Hoshik Kim said data centers now absorb roughly 70% of global DRAM output, and that “this time is different” — the industry may be structurally undersupplied for years rather than cycling normally. Whether that reflects genuine demand or an AI bubble came up repeatedly in panel discussions, with analyst David Kanter noting Anthropic has turned cash-flow positive as evidence the shift is real. Intel, Samsung, and TSMC’s dueling process announcements (18A-P, A16, and new CFET architectures, respectively) rounded out a symposium whose consistent message, per Intel’s Chris Auth, was that “we have just scratched the surface with hybrid bonding” — and that EDA tools now need to be thermally aware from the start.

Click here to read the full article in Semiconductor Digest magazine.