$Taiwan Semiconductor(TSM.US) TSMC does not produce a single DRAM chip, yet it is becoming central to high‑performance HBM. From HBM4 onward, two critical steps — a customized base layer and co‑packaging of memory with the GPU — run through TSMC's lines.
Entry 1: the base layer. It serves as the bottom‑stack 'relay station' in HBM. HBM3e and earlier used simpler 20nm flows that DRAM vendors could make in‑house; with HBM4, nodes move to 12nm and flagships to 2/3nm, forcing outsourced fab to TSMC (Samsung can self‑manufacture).
The bar is higher because a doubled bus width raises PHY precision requirements, and functions like the memory controller that lived in the XPU are migrating to the base layer. As the base layer shifts from off‑the‑shelf to customer‑specific parts — e.g., NVDA's NVHBM uses a proprietary protocol claiming +30% bandwidth and −15% power — reliance on TSMC's advanced nodes deepens.
Entry 2: CoWoS packaging. HBM's high bandwidth depends on co‑packaging with the XPU on a silicon interposer, primarily via TSMC's CoWoS, where CoWoS‑L is already mainstream with a >60% share.
Capacity cadence matters more: DRAM wafers will not meaningfully free up until 2027 (+15%~20%), while CoWoS capacity in 2027 doubles vs. 2026 — packaging is expanding faster than DRAM bits.The bottleneck and value are shifting toward packaging and foundry. How much HBM a DRAM vendor can deliver now depends not only on its own lines, but also on how much base‑layer wafer capacity and CoWoS slots it can lock at TSMC.
Take SK hynix's HBM4: it only handles die fabrication and stacking, while the base layer is co‑designed with NVDA and manufactured by TSMC, and final packaging is also completed at TSMC. If the industry moves toward 'fewer layers, more dies', it saves DRAM wafers but consumes more packaging capacity.
The choke point shifts further from 'DRAM vendor expansion' to 'TSMC ramp'.
