J.P. Morgan: TSMC CoWoS CoWoS Capacity Expansion&g

J.P. Morgan: TSMC CoWoS

CoWoS Capacity Expansion

> Capacity Increase: J.P. Morgan is raising its CoWoS capacity estimates for 2026–2028 by 1%, 9%, and 11% respectively.

> Targets: TSMC’s CoWoS capacity is expected to reach 115k, 190k, and 225k wafers per month (wfpm) by the end of 2026, 2027, and 2028.

> Strategic Shifts: TSMC is accelerating expansion at AP7 Phase 2 (reallocating capacity from SoIC to CoWoS) and is selectively outsourcing interposer manufacturing to Vanguard.

> OSAT Role: Capacity for CoWoS-like processes at Outsourced Semiconductor Assembly and Test (OSAT) providers is expected to reach 15k, 50k, and 85k wfpm by the end of 2026, 2027, and 2028, primarily to support server CPU packaging.

3D SoIC and CoPoS Outlook

> 3D SoIC: The capacity ramp is now more focused on 2028 (projected 65k wfpm) to align with mass adoption in accelerators. While 2027 may see a slight push-out to accommodate CoWoS demand, key customers like AWS, OpenAI, Meta, and NVIDIA (Feynman versions) are expected to adopt SoIC in 2028.

> CoPoS: This technology is currently in the engineering stage. Risk production is expected in early 2028, with mass production likely in 2029.

Customer Demand and Forecasts

> NVIDIA: CoWoS allocations for NVIDIA are rising, reflecting strong demand for new CPUs (Vera in 2027, Rosa in 2028) and accelerators. All NVIDIA accelerator and Co-Packaged Optics (CPO) products are on CoWoS-L at TSMC.

> AMD: Estimates for AMD are rising significantly in 2027–2028, driven by the Venice server CPU family, which will largely utilize a CoWoS-L-like process from ASE.

> CPUs and ASICs: Server CPUs (e.g., NVDA Vera, AMD Venice) have emerged as a primary upside catalyst for CoWoS demand in 2027. Other programs like Google’s TPU and AWS’s Trainium continue to ramp, though ASICs for companies like Microsoft and Meta remain at a smaller scale.

> Supply Chain Roles: AWS and Alchip are expected to remain the primary suppliers for the Neuronlink and UALink versions of Trainium 4. Marvell may take on some share for specific variants that utilize "NVLink fusion" based interconnects. While Trainium 4 volumes in 2028 are expected to be relatively flat compared to Trainium 3 volumes in 2027, the wafer consumption and average selling prices (ASPs) for these chips are expected to be significantly higher.

> 2027 as a Key Ramp Year: While TPU and Trainium are currently the only large-scale ASIC programs, 2027 is viewed as a key year for others to ramp, with a heavy focus on Meta’s MTIA and Microsoft’s Maia.

Other Technological Notes

> Intel EMIB: Intel’s EMIB-T process is seeing incremental demand, notably for the MediaTek TPUv9 Humufish. However, substrate capacity remains a limiting factor for this process. Intel’s EMIB process is positioned as a cheaper alternative, with costs estimated at approximately 50% of TSMC's CoWoS-L packaging technology. Current substrate-level yields for the EMIB process are around 60%, which is considered acceptable by the researchers for a process 1–1.5 years away from ramp. However, substrate capacity is viewed as a key limiting factor for capacity expansion because the processes for substrate build-up and embedding the silicon bridge steps currently have low yields.

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