SK hynix: After Standard HBM Expansion, Is Customization the Next Act?

Memory stocks have recently come under pressure as investors fall back on a familiar cyclical script: a concentrated wave of capacity arrives in 2027–2028, supply catches up with demand, prices peak, and valuation multiples de-rate.

That view treats memory as a standardized commodity — something interchangeable and made by anyone. But the underlying technology is changing. In hardware, some products are designed simply to operate reliably within conventional parameters; others push beyond those limits to deliver materially higher performance and efficiency.

In the CPU era, Intel handled mainstream workloads while AMD repeatedly competed at the performance edge, particularly in gaming. In the GPU era, NVIDIA captured the gateway to general-purpose GPU model training, while AMD and custom-silicon specialists such as Broadcom and Marvell began competing for AI inference workloads.

HBM is now moving through a similar three-step evolution.

1. Process shift: HBM4

The base die is moving from a DRAM process to a logic process. HBM interface bandwidth roughly doubles with each generation — from 1,024 bits in HBM3 to 2,048 bits in HBM4 — and all data flows through this base die.

SK hynix is using TSMC’s 12nm logic process, while Samsung is using its own 4nm foundry process. Micron, balancing cost, is expected to keep HBM4 on a DRAM process before moving HBM4E to a TSMC logic process. At this stage, however, the product design still largely belongs to the memory manufacturer.

2. Custom HBM: the inflection point

Custom HBM, or cHBM, pushes the GPU-side memory controller and interface circuitry down into the base die. This frees valuable GPU area for compute and allows preprocessing, compression and data movement to happen closer to the memory, reducing power consumption.

There are several possible design models: a memory supplier can build to a customer’s specification; an ASIC partner such as Marvell can work with the three major memory manufacturers; or the customer can design the logic itself, as NVIDIA may do.

Once customer-specific logic is embedded in the base die, that HBM stack becomes a dedicated component. It cannot readily be sold to another customer, and the customer cannot easily switch suppliers. A standardized part begins to turn into a customer-locked, scarce strategic resource.

3. Memory-on-logic

At the cHBM stage, the base die already resembles a customer-specific logic chip. The next step is to remove the standalone base die and place the memory stack directly on top of the compute die.

Interconnect density could rise from tens of thousands of contact points to hundreds of thousands, while signal paths shrink from millimetres to tens of micrometres. The potential benefits are lower latency and much higher data throughput.

The biggest unresolved issue is heat. DRAM stacked on top of a compute die consuming hundreds of watts can block the heat path while absorbing heat itself. At elevated temperatures, refresh intervals shorten and performance can deteriorate. Thermal management may therefore determine whether memory-on-logic becomes commercially viable.

For the next several years, cHBM appears to be the more realistic commercial path. Memory-on-logic is more ambitious and will likely need further progress in thermals and manufacturing yield. The two approaches may develop in parallel while their roadmaps are validated.

Industry progress is already visible

Custom HBM has entered official roadmaps. NVIDIA’s Feynman generation is rumoured to use cHBM around 2028, although this has not been officially confirmed. Samsung, SK hynix and Micron have all added custom HBM to their research roadmaps, and Marvell has announced joint development work with the three major memory suppliers.

Memory-on-logic also has an early commercial analogue. At its June 2026 Investor Day, Qualcomm introduced HBC for its AI250 accelerator, which is planned for volume production in mid-2027. HBC uses LPDDR rather than HBM, and the lower die is a purpose-built near-memory accelerator rather than the GPU itself. The architecture is designed to reduce dependence on both HBM supply and advanced packaging capacity.

Qualcomm says the combination of a low-power accelerator and low-power LPDDR can deliver six times the bandwidth per watt of HBM and 200 times the capacity per watt of on-chip SRAM. These claims still need to be validated on production hardware.

Saudi Arabia’s HUMAIN has included AI250 racks in its deployment plans, while reports have also cited Microsoft CEO Satya Nadella discussing Qualcomm HBC deployment in Azure. Separately, SK hynix has reportedly been discussing direct HBM-on-processor stacking with NVIDIA and other fabless companies since 2023, while Taiwanese ASIC designer GUC has proposed a DRAM-on-Logic architecture.

The valuation question

Bulls are looking for the point at which memory’s business model may be re-rated. The closer memory moves toward custom silicon, the easier it becomes to move away from the economics of a commodity product.

If the three major memory manufacturers remain purely cyclical businesses, investors will continue to focus on bit growth and ASP pricing. But the revenue mix and margin impact of customization have not yet appeared clearly in reported financials — and therefore are not yet embedded in most valuation models.

That may be where the upside has not yet been fully priced in.

What is your view on SK hynix after its latest results? Does customization meaningfully weaken the traditional memory cycle, or will capacity and pricing still dominate the investment case?

This content is for information and discussion only and does not constitute investment advice.

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