---
title: "Track Hyper | Intel's foundry strategy accelerates: Countdown to 18A mass production"
type: "News"
locale: "zh-CN"
url: "https://longbridge.com/zh-CN/news/238662833.md"
description: "14A aims at Taiwan Semiconductor, reconstructing the industry landscape through ecological layout"
datetime: "2025-05-04T01:20:10.000Z"
locales:
  - [zh-CN](https://longbridge.com/zh-CN/news/238662833.md)
  - [en](https://longbridge.com/en/news/238662833.md)
  - [zh-HK](https://longbridge.com/zh-HK/news/238662833.md)
---

> 支持的语言: [English](https://longbridge.com/en/news/238662833.md) | [繁體中文](https://longbridge.com/zh-HK/news/238662833.md)


# Track Hyper | Intel's foundry strategy accelerates: Countdown to 18A mass production

Author: Zhou Yuan / Wall Street News

At the Intel Foundry Direct Connect in 2025, Intel announced the latest progress of its "Five Process Nodes in Four Years" plan, marking a critical implementation phase for Intel's foundry strategy.

Intel's CEO Lip-Bu Tan shared the progress and future development focus of Intel's foundry during the opening speech, emphasizing that Intel is pushing its foundry strategy into the next stage.

Intel's foundry services also include mature nodes, having completed its first 16nm production wafer in the fab, and Intel is also attracting customers with the 12nm node developed in collaboration with United Microelectronics Corporation.

However, the main focus of Intel's foundry services is the implementation of advanced process nodes: currently, the Intel 18A process node has entered the risk production stage, with defect density continuously optimized; Intel plans to achieve mass production by the end of 2025.

This node uses Power Via backside power supply technology, with a 20% increase in transistor density compared to the previous generation and a 10%-15% performance improvement, primarily targeting high-end markets such as AI chips, high-performance computing (HPC), and autonomous driving domain controllers.

As the core product of Intel's foundry strategy, the mass production of Intel 18A will directly compete with TSMC's 2nm (N2) and Samsung's SF2 nodes.

TSMC's N2 process is expected to enter mass production in the second half of 2025, while Samsung's SF2 node is planned for release in 2025.

With the technological advantages of the 18A node, Intel has attracted top customers such as NVIDIA, Broadcom, and MediaTek to conduct wafer testing, with NVIDIA planning to develop the next generation of AI accelerator cards based on the 18A process.

In terms of next-generation process layout, Intel announced that Intel 14A (1.4nm) has initiated customer collaboration and sent out early PDK (Process Design Kit), which includes a set of data, documents, and design rules for designing and verifying processor designs.

According to Intel, the 14A process is expected to enter mass production in 2027, one year ahead of TSMC's A14 process (expected mass production in 2028).

Intel 14A is the next generation product following 18A, and if everything goes smoothly, 14A will become the industry's first node to adopt high numerical aperture EUV lithography technology.

The 14A process will use Power Direct contact power supply technology, combined with the second-generation Ribbon FET transistor architecture, achieving a 15%-20% performance improvement per watt.

Additionally, Intel 14A will introduce new Turbo Cell technology, allowing designers to dynamically optimize the balance between performance and power consumption within chip modules, aiming to further enhance chip speed, "including CPU maximum frequency and GPU critical path," to strengthen Intel's competitiveness in the AI and HPC fields.

Intel stated in a release, "Turbo Cells achieve a balance between power consumption, performance, and area for target applications." Intel emphasized that it has already put its second High NA EUV equipment into operation for Intel 14AThis device starts up much faster than the first device.

In the face of competition from TSMC's SoIC and Samsung's X-Cube, Intel is building system-level integration capabilities through Foveros Direct 3D stacking and EMIB 2.5D bridging technology.

At Intel Foundry Direct Connect, Intel showcased a large-scale Chiplet solution based on EMIB-T technology, which can integrate 4 compute dies and 12 HBM5 memory, supporting a package size of 120mm×120mm, meeting the high bandwidth memory requirements of AI chips.

Additionally, Foveros-R and Foveros-B technologies are expected to enter mass production in 2027, further enhancing packaging flexibility and energy efficiency.

In terms of supply chain collaboration, Intel has partnered with Amkor Technology to incorporate Amkor's packaging capacity into the foundry ecosystem, providing customers with more packaging technology options.

This "process + packaging" collaborative model forms Intel's full-chain service capability for customers, from chip design to system integration: for example, the AI chip customized for NVIDIA can achieve 3D stacking through Foveros Direct, increasing computing density by over 30%.

Through a globally diversified manufacturing network, Intel's strategy to address supply chain risks is in place; Intel's Oregon wafer fab has initiated mass production of Intel 18A, and the Arizona Fab 52 plant has completed tape-out, planning to enter the mass production ramp-up phase by the end of 2025.

The 12nm node developed in collaboration with UMC is expected to complete validation in 2026 and enter mass production in 2027, primarily serving the IoT and automotive electronics markets.

In terms of capital investment, Intel has invested a total of $90 billion over the past four years, with $37 billion allocated for wafer fab equipment, and EUV capacity in Arizona and Israel wafer fabs has increased by 100% and 50%, respectively.

This aggressive capacity expansion strategy will increase its automotive-grade memory packaging capacity by 50% by 2025, with monthly production capacity exceeding 15 million units.

The Intel Foundry Accelerator Alliance has added two new projects: the Chiplet Alliance and the Value Chain Alliance.

The Chiplet Alliance focuses on defining interoperable and secure chiplet standards, supporting customers in developing heterogeneous integrated products based on Chiplet technology, such as interconnecting compute dies based on Intel 18A with HBM high bandwidth memory through the UCIe interface.

The Value Chain Alliance integrates IP, EDA, and design service resources to provide customers with a one-stop solution from process design to mass production, with partners like Synopsys and Cadence already providing EDA tools and reference flows for Intel 18A.

In terms of customer expansion, Intel's 16nm products developed in collaboration with MediaTek have entered wafer fab production, and deep cooperation is underway with companies like Microsoft and Qualcomm in the fields of AI chips and autonomous driving domain controllersThis ecological synergy model allows Intel to increase its share of automotive-grade storage revenue to 12% in 2024, with plans to further break through to 15% in 2025.

Currently, the global wafer foundry market is characterized by "TSMC leading, Samsung catching up, and Intel breaking through."

According to TrendForce research data, TSMC holds the top position with a 67% share, Samsung is second with 10%, while Intel only accounts for 1%. In the AI chip foundry sector, TSMC occupies 68% of the market, with Intel holding just 5%.

To break this pattern, Intel has adopted a strategy of "technological differentiation + ecological bundling."

At the process level, Intel's 18A reduces resistance loss through PowerVia technology, optimizing power consumption by 10% compared to TSMC's N2 node; in the packaging stage, Foveros Direct's 3D stacking technology enables higher integration density, such as integrating CPU, GPU, and HBM memory within a single package, reducing the area by 40% compared to traditional 2D designs.

Currently, Intel's foundry strategy still faces three core challenges.

First is the risk of technology validation; the yield improvement and customer certification progress of Intel's 18A may not meet expectations. TSMC's N2 node yield has reached 80%, while Intel's 18A is still in the risk trial production stage.

Second, there are ecological barriers; TSMC locks in major clients like NVIDIA and AMD through a combination of "CoWoS + packaging + 3nm process," and Intel needs to break through customer trust barriers in the AI chip field.

Finally, there is financial pressure; Intel's foundry business is expected to lose $13.4 billion in 2024, and if the mass production of 18A does not meet expectations, it may lead to further deterioration of cash flow.

The technological breakthroughs and ecological layout showcased by Intel at the 2025 Foundry Conference signify that it is reconstructing the industry landscape with a four-dimensional strategy of "process + packaging + manufacturing + ecology."

Despite facing the monopoly pressure from TSMC and internal financial challenges, Intel is gradually establishing a differentiated advantage in the AI chip and automotive-grade storage sectors through the mass production of 18A, 14A technology reserves, and global capacity expansion.

If it can continue to make breakthroughs in customer certification and yield improvement, Intel is expected to achieve its goal of becoming "the second-largest foundry in the world" by 2030, bringing new competitive variables to the semiconductor industry

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