---
title: "The chip inflation wave is spreading, and Morgan Stanley expects that \"backend testing and packaging factories\" will raise prices in 2026, marking the first increase since the pandemic"
type: "News"
locale: "zh-CN"
url: "https://longbridge.com/zh-CN/news/263243860.md"
description: "Morgan Stanley warned that the strong demand for AI semiconductors is severely squeezing packaging and testing capacity, forcing backend manufacturers to have stronger bargaining power. Influenced by three major factors, the price of advanced packaging is expected to rise by 5-10% in 2026, marking the first price upcycle since the chip shortage during the COVID-19 pandemic. Leading manufacturers in Taiwan, ASE and KYEC, will spearhead this price increase"
datetime: "2025-10-29T08:54:03.000Z"
locales:
  - [zh-CN](https://longbridge.com/zh-CN/news/263243860.md)
  - [en](https://longbridge.com/en/news/263243860.md)
  - [zh-HK](https://longbridge.com/zh-HK/news/263243860.md)
---

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# The chip inflation wave is spreading, and Morgan Stanley expects that "backend testing and packaging factories" will raise prices in 2026, marking the first increase since the pandemic

Author: Xu Chao

Source: Hard AI

Morgan Stanley stated that the wave of semiconductor inflation, which began with wafer foundry and memory, is spreading downstream. Chip backend packaging and testing (OSAT) manufacturers are preparing for the first price increase cycle since the COVID-19 pandemic.

Morgan Stanley warned that the strong demand for AI semiconductors is severely squeezing packaging and testing capacity, forcing backend manufacturers to have stronger bargaining power. Leading manufacturers in Taiwan, ASE and KYEC, will lead this price increase.

Analysts expect that due to three major factors, the price of advanced packaging will rise by 5-10% by 2026, marking the first price upcycle since the chip shortage caused by the COVID-19 pandemic:

> 1.  Strong AI demand, TSMC's CoWoS capacity overflow is rapidly filling ASE's CoWoS capacity and KYEC's testing capacity.
>     
> 2.  Capacity constraints, ASE and KYEC need to reject lower-margin products or shift capacity from non-AI semiconductor wire-bonding to AI semiconductor flip chip.
>     
> 3.  Material cost inflation (gold, copper, BT substrates).
>     

## Capacity Tightening Driven by AI

Morgan Stanley's analysis believes that capacity tightness is the core driving force behind this price increase. As TSMC's CoWoS capacity is in short supply, its orders are significantly overflowing to manufacturers like ASE.

Analysts stated that **ASE's capacity utilization rate (UTR) for the third quarter of 2025 has reached 90%, which effectively constitutes a shortage and provides strong leverage for price negotiations in 2026.** To meet AI-related demand, ASE is even shifting some wire-bonding capacity to higher-margin flip chip packaging.

Based on this optimistic outlook, Morgan Stanley has raised the earnings expectations and target prices for related companies, increasing the target prices for ASE and KYEC to NT$228 and NT$218, respectively, while reiterating an "overweight" rating.

However, the report also pointed out that this optimistic sentiment is not "shared equally," as Morgan Stanley maintains a "reduce" rating on JCET due to fierce competition from domestic peers in mainland China and lower capacity utilization rates

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- [JCET (600584.CN)](https://longbridge.com/zh-CN/quote/600584.CN.md)
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- [Direxion Semicon Bull 3X (SOXL.US)](https://longbridge.com/zh-CN/quote/SOXL.US.md)

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