<div id="readability-page-1"><div><p>DNP announced the development of a nanoimprint lithography (NIL) template featuring a circuit line width of 10 nanometers (nm: 10-9 meter). The new template enables patterning for logic semiconductors equivalent to the 1.4nm generation and meets the miniaturization needs of cutting-edge logic semiconductors. In line with the shift to more sophisticated devices seen in recent years, demands have emerged for even greater miniaturization in cutting-edge semiconductors, leading to advances in Extreme Ultra-Violet (EUV) lithography-based production.</p><p>EUV lithography, however, requires substantial capital investment, energy consumption, and operating costs in building production lines and the exposure process. Since 2003, DNP has been developing NIL templates and has successfully accumulated extensive know-how in high-precision patterning. In this latest development, DNP has developed a NIL template with a 10nm line pattern.</p><p>It can replace a portion of the EUV lithography process, facilitating the manufacture of cutting-edge logic semic Conductors for clients that do not have EUV lithography production processing. Key Features: DNP has successfully achieved the new NIL template with a circuit line width of 10nm by leveraging Self-Aligned Double Patterning (SADP), which doubles pattern density through film deposition and etching a pattern formed by the lithography device. The technology also reduces power consumption in the exposure process of cutting-edge semiconductor manufacturing.</p><p>Driven by an energy-saving processing technology for ultra-fine semiconductors using NIL, it is now possible to reduce power consumption to approximately one-tenth of currently available exposure processes, such as Argon Fluoride (ArF) immersion and EUV.</p></div></div>

大日本印刷(ADR)

半導體 3 倍做多 - Direxion

<p>大日本印刷 (ADR) 開發了一種具有 10 納米線條圖案分辨率的納米壓印光刻模板，適用於尖端半導體。這種模板支持微型化需求，並可以替代部分 EUV 光刻工藝，顯著降低能耗。該技術利用自對準雙圖案化，增強了半導體制造中的圖案密度和能效</p>

大日本印刷 (ADR) 在用於尖端半導體的納米壓印模板上成功實現了 10 納米線條圖案分辨率