--- title: "Alibaba Marches Upward to the AI Core Chip High Ground" type: "News" locale: "zh-HK" url: "https://longbridge.com/zh-HK/news/280392081.md" description: "RISC-V transitions from a 'spare tire' to a primary option overnight" datetime: "2026-03-25T01:18:23.000Z" locales: - [zh-CN](https://longbridge.com/zh-CN/news/280392081.md) - [en](https://longbridge.com/en/news/280392081.md) - [zh-HK](https://longbridge.com/zh-HK/news/280392081.md) --- > 支持的語言: [简体中文](https://longbridge.com/zh-CN/news/280392081.md) | [English](https://longbridge.com/en/news/280392081.md) # Alibaba Marches Upward to the AI Core Chip High Ground ![Image](https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/b8c31d76-4622-44d3-8e60-d253920207d5.png?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg) The Agent craze, ignited by OpenCLAW's 'lobster' at the start of the year, needs no further introduction. The potential semiconductor demand it brings has already propelled many "shovel sellers" to stardom. On March 24th, Alibaba's DAMO Academy unveiled its significant chip products – the new flagship CPU XuanTie C950 and the high-efficiency CPU XuanTie C925. Their direction is clear: directly targeting the hardware demands of the exploding AI-Agent market this year. Industry insiders believe that, measured by parameters like clock speed, this marks the first time a CPU based on the open-source RISC-V architecture has achieved single-core performance truly comparable to earlier generations of ARM's high-end/x86 processors, reaching the single-thread performance of commercially viable server CPUs. RISC-V was previously perceived more as low-end, edge, and lightweight. After the era of Agentic AI, changes are happening. Previously, AI bottlenecks were concentrated in GPU computing power. However, in the Agentic AI phase, bottlenecks are beginning to spread to memory, I/O, and system scheduling, shifting the computing paradigm from a single GPU to heterogeneous architectures. Unlike traditional computing chips that pursue FLOPS, these RISC-V CPUs no longer emphasize faster computation but are responsible for organizing distributed computing power, becoming the central hub for AI system operation. Lu Da, Chairman of the RISC-V International Foundation, stated directly to Wall Street News, "There is currently a significant demand in the market for major international companies to develop RISC-V as their primary product." For Alibaba's DAMO Academy, years of patient accumulation have finally led to a moment of realization, capitalizing on immense opportunities. ![Image](https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/f1dbe49f-edaf-4e82-8b3a-a1e80df25b8b.jpeg?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg) ## Aiming for High-End In the AI Agent era, Alibaba aims to define the high-end CPU role amidst new demands. On March 24th, Alibaba's DAMO Academy released its new generation flagship CPU product, XuanTie C950. It adopts the open-source RISC-V architecture. Furthermore, leveraging RISC-V's open and flexible nature, XuanTie C950 integrates a self-developed AI acceleration engine, offering native support for large models with hundreds of billions of parameters, such as Qwen3 and DeepSeekV3. Unlike traditional closed-source architectures, RISC-V, being open-source, flexible, and customizable, is widely considered a new architecture "born for AI" that could reshape the current chip industry landscape. RISC-V has truly taken a step towards high-end computing. For instance, the XuanTie C950 has broken the 70-point barrier in the SPECint2006 benchmark test, achieving over 22/GHz in single-core performance with a maximum clock speed of 3.2GHz, and has also smoothly run large models with hundreds of billions of parameters for the first time. This effectively sheds the low-end label of RISC-V and enters the two most critical sectors: high-performance computing and AI computing. Industry insiders believe that if RISC-V can establish a foothold in high-performance and AI scenarios, it will cease to be merely a cheap and flexible alternative and will begin to influence the division of labor within the entire chip ecosystem, competing directly with x86 and Arm for architectural dominance. What's most noteworthy about the C950 this time isn't just its performance, but its "usability." Many chip promotions focus on extreme performance, but what truly determines scalability is whether it can run stably under real-world workloads. DAMO Academy conducted joint tests using classic server workloads like MySQL, Redis, Nginx, and OpenSSL. The results show that with software and hardware co-optimization, the C950's performance has reached the industry's first-tier level, with cloud network and cloud storage performance improving by over 30% compared to some mainstream products. This means the C950 is not just suitable for laboratories but is attempting to enter more realistic scenarios like cloud computing, generative AI, high-end computing, and edge computing. Additionally, its support for all standard and optional extensions of RVA23.1 means it is beginning to align with server-grade, automotive-grade, and AI-grade platforms in terms of software ecosystem, system compatibility, and platform adaptability. For RISC-V, this standardization capability is crucial as it determines whether the architecture can truly enter mainstream operating systems and industries. Meng Jianyì, Chief Scientist at Alibaba DAMO Academy, stated that although RISC-V has widely penetrated intelligent terminals, automotive, home appliances, communications, and other fields, it has long suffered from insufficient performance and software ecosystem barriers. Only by launching high-performance benchmark products can RISC-V truly seize the opportunities of the AI era and compete on the same stage with traditional architectures, opening up the application market. This is precisely why the market places such significant importance on the new generation flagship CPU, XuanTie C950, released by Alibaba DAMO Academy today. ## Years of Dormancy Initially, the market viewed AI computing power as exclusively GPU's domain, but the Agentic AI era is different. When the system involves not just one person using a computer but countless intelligent agents running simultaneously, token call volume, KV-Cache loading, first-token latency, and task serialization/concurrency switching all elevate the importance of the CPU. Meng Jianyì emphasized that as model capabilities have crossed a threshold, there will be a large number of tasks interacting with AI in the future. This necessitates new changes in CPU architecture, requiring CPUs to be redesigned for the AI era. In this context, the CPU is no longer a supporting role next to the GPU but becomes the central hub for system task scheduling and data flow. DAMO Academy is precisely moving in this direction. They have released two RISC-V native AI computing engines: a 4K ultra-wide Vector engine and a Matrix engine, unified with the CPU's addressing. The aim is to eliminate data copy bottlenecks and natively integrate general-purpose computing with AI computing power. More critically, it can now smoothly run the industry's top-tier Qwen3 open-source model and the full-featured version of DeepSeekV3, which has extremely high computing requirements: Qwen3 outputs at 34 tokens/s with a first-token latency of 3.4 seconds; DeepSeekV3 outputs at 18 tokens/s with a first-token latency of 1.7 seconds. This signifies that RISC-V CPUs can natively support large models with hundreds of billions of parameters for the first time. This represents a shift in architectural positioning: RISC-V is moving from a general-purpose CPU towards becoming the new computing hub for the AI Agent era. Meng Jianyì revealed that inference work is currently underway. Qwen has various models, and the first iteration of each model will be adapted to XuanTie first. This implies that RISC-V CPUs can natively support large models with hundreds of billions of parameters for the first time, marking a change in architectural positioning: RISC-V is transitioning from a general-purpose CPU to the new computing hub for the AI Agent era. In fact, Alibaba didn't just start working on RISC-V today. Since 2018, Alibaba has been one of the earliest teams in China to invest in RISC-V. The XuanTie C910 released in 2019 was already one of the highest-performing RISC-V CPU IPs in the industry at the time, breaking the 2GHz barrier and pushing Specint2k6 to 7/GHz. Even then, the market began to realize that RISC-V didn't have an inherent performance ceiling. Later, the C910 began to see real-world implementation. Huang Shaorui, General Manager of Allwinner Technology's Product R&D Center, recalled that they started applying RISC-V in their products in 2019. At that time, they experienced significant difficulties due to the immaturity of the software. However, with the development of the ecosystem, the related support and deployment are now almost readily available. In 2024, DAMO Academy, in collaboration with the Institute of Software, Chinese Academy of Sciences, developed the world's first stably operating RISC-V laptop. European cloud service provider Scaleway also launched the world's first RISC-V cloud instance. The underlying computing base for these came from the C910. Subsequently, the XuanTie C930, released in 2025, crossed the entry threshold for server chips. Following this path, it becomes clear that Alibaba's XuanTie has been consistently focused on pushing RISC-V towards high performance, commercial viability, and server-grade capabilities, rather than chasing fleeting trends. Meng Jianyì admitted that the cycle from standardizing to IP and then to mass production of chips is very long. Facing practical bottlenecks, leading companies must endure solitude and make long-term, substantial investments, focusing on the ecological value of the next five to ten years. ## Ecosystem Grand Play The true moat is not just the CPU itself but a synergistic construction of architecture, ecosystem, standards, and industry collaboration. Alibaba is now building a complete open ecosystem around RISC-V. DAMO Academy has released the Flex platform, packaging processor modeling, development environments, and software toolchains into a comprehensive capability. This allows customers to use standardized, high-performance XuanTie CPUs as a foundation and also perform deep custom modifications based on it. Last year, XuanTie supported 35 customers in making 38 underlying CPU modifications. More than half of these customization requests were concentrated in areas like AI acceleration, storage optimization, and reliability enhancement. This indicates that Alibaba is not merely selling IPs but is platformizing its chip design capabilities. Regarding the issue of fragmentation due to customization, Lu Dai believes that RISC-V's greatest advantage lies in its flexible customization. Many official standards evolve from these independently explored extensions. Therefore, standardization will not hinder innovation; instead, it is an iterative capability within an open system. Meng Jianyì echoed similar views, stating that the ecosystem requires underlying operating systems to adhere to standards. The freedom for innovation left above the standards is precisely what drives RISC-V to be continuously, self-consistently, and vibrantly innovative. For industrial clients, this lowers the barrier to entry for high-end custom chips. For the RISC-V ecosystem, this means it is no longer just an open-source idealism but is beginning to have a path for industrial implementation. Huang Shaorui mentioned to Wall Street News that as products like intelligent robots increasingly demand general-purpose computing power, such as the demand for multi-core products for deploying models like "lobster," Allwinner chose XuanTie precisely because of its long-term, continuous investment and comprehensive capabilities that closely match its terminal SOC product matrix. Jiang Tao, Vice President of Resource Development at Sophon Technologies, cited complex power supply chips as an example, pointing out that without the support of DAMO Academy's open-source ecosystem kernel, traditional power companies would find it difficult to cope with the digital challenges brought about by soaring computing power. Although RISC-V is still like a "youth" that needs joint support, its highly competitive cost and modular flexibility have become powerful tools for enterprises to develop high-end product lines and achieve a breakthrough. Simultaneously, Alibaba XuanTie is deeply involved in the work of the RISC-V International Foundation at the standard level, leading the formulation of server-grade chip standards, participating in key specifications like BRS and RPMI, and promoting discussions within the Matrix extension community. As Meng Jianyì said, they have overcome the drawbacks of traditional NPUs being difficult to form an ecosystem, choosing to build AI acceleration engines based on standards like RVV within the larger RISC-V ecosystem, laying the foundation for long-term ecological prosperity. This is no longer a simple product competition but a battle for ecosystem influence. _The following is a transcript of the dialogue with Meng Jianyì, Chief Scientist at Alibaba DAMO Academy; Lu Dai, Chairman of the RISC-V International Foundation; Xiao Jianhong, CEO of Chipsea Technologies; Jiang Tao, Vice President of Resource Development at Sophon Technologies; and Huang Shaorui, General Manager of Allwinner Technology's Product R&D Center:_ **36Kr Tech:** What are the current practical bottlenecks in RISC-V development? **Meng Jianyì:** The practical bottleneck is still time. Because the entire cycle of turning a RISC-V standard into an IP, then into a chip, and then scaling the chip takes time. Therefore, this is our fourth XuanTie Ecosystem Conference, the previous one was also held in Shanghai. After four years, their products will ship one hundred million RISC-V units annually. With about a hundred such companies, the user base will be established. So, the time is four years, and we started cooperating at that time. **36Kr Tech:** NVIDIA's GTC just concluded, and it's evident that the era of large models is driving tremendous changes in computing power demand. They also introduced CPUs specifically for data centers. How will we address the fine-grained changes in current computing power needs? **Meng Jianyì:** Inference will certainly be a major area this year, and everyone sees that model capabilities have crossed a threshold. Therefore, models need to be used more deeply. If developed into productivity tools, they become Agentic AI today. We need extensive interaction with AI, which means you have many tasks, such as retrieving data from your database, searching for corresponding data online, then storing it back into the database, and so on. Jensen Huang, in his presentation, spoke about the bottlenecks in this area. Today, he believes that new CPUs are needed for AI. He refers to his Vera, which incorporates many features, such as strong computational requirements, mandatory security, and excellent IO capabilities. This is his redefinition of CPU architecture. Moreover, previously, our CPUs were large server sockets; now, they have brought two closely together to create a large chip. So, overall, CPU architectures are undergoing new changes. Therefore, I believe that in the AI era, CPUs need to be redesigned. Second, regarding AI computing power, these are things everyone is already working on. **36Kr Tech:** What are the current plans? **Meng Jianyì:** Our XuanTie C950 is optimized for this direction. We have high performance, excellent access capabilities, and security – all of which are moving in this direction. **36Kr Tech:** We are now in a transitional phase towards Physical AI. RISC-V chips have accumulated extensive experience in the IoT domain. In the era of Physical AI, what relative opportunities do RISC-V chips now have compared to other chips? **Huang Shaorui:** Allwinner Technology primarily focuses on terminal-side and edge-side products. We started applying RISC-V in our products many years ago, around 2019. Over these past few years, as we've developed products, we've found that RISC-V's development and changes have been extremely rapid. Since 2019, when we started, developing products and software was very painful because the entire RISC-V ecosystem was very immature. Of course, in recent years, our company has used RISC-V as the main controller in numerous products. The entire software ecosystem has undergone significant changes, including the kernel, middleware, supporting software, and AI deployment, which are now almost readily available. If I want to develop a new product, I need new "low-cost" software, and companies have essentially completed the basic functions of RISC-V. From the perspective of RISC-V terminal applications, one area is robotic products, which require general-purpose CPUs on the terminal side plus some small AI capabilities. The second area is that the demand for general computing power is still at a relatively low level, but the demand for general computing power in products is gradually expanding. For example, to deploy "Lobster," which previously required three-core or four-core products, we now need four-core or eight-core products. The demand for general computing power in these scenarios is also increasing. I believe these two areas represent future points for large-scale RISC-V adoption. **Meng Jianyì:** Physical AI is a more distant concept, even more challenging than Agentic AI, which we are discussing today. It requires interaction with the entire physical world, so Physical AI chips essentially solve problems on a single chip, with very high energy efficiency requirements. RISC-V is indeed exploring this path. Previously, in data centers, we often used a CPU with many GPUs or a large cluster. However, for Physical AI, the demand for computing efficiency is even higher. Therefore, today, our opportunity lies in adapting more advanced or open architectures to the rapid evolution of Physical AI models, which is a very important opportunity. **36Kr Tech:** Are there any major clients currently trying to use RISC-V chips? **Lu Dai:** I mentioned earlier that we hope for a major company to take the lead. In China, Alibaba is doing well, and there are many RISC-V companies. However, there is currently a significant demand to see major international established companies also develop RISC-V as a main product. This will make a big difference. **36Kr Tech:** Are the current Qwen models using XuanTie chips for inference and training? **Meng Jianyì:** Training is definitely not done, but inference is ongoing. Many models are using Qwen. Since Qwen is part of our Wujian Alliance, the first iteration of each model is always adapted to XuanTie first. **36Kr Tech:** Does Shanghai have advantages in terms of open-source community ecosystems? **Xiao Jianhong:** China's semiconductor industry has developed very rapidly over the past five years. It used to be difficult to publish a paper at international top semiconductor conferences; now, nearly a third come from China. Therefore, regarding the development of China's semiconductor industry, I have been personally involved since returning to China to start my business in 2017. Over these years, I have gained insights into Shanghai's semiconductor development. I can say that almost all excellent companies have R&D presence in Shanghai, if not their headquarters. Secondly, regarding market thinking, whether it's absorbing new ideas, growing, or promoting them in the market, this aggressive approach is inconsistent with the traditional perception of Shanghai. Thirdly, regarding open source, I decided in 2020. At that time, when we were just starting to design chips, we wanted to use RISC-V. Later, we were among the earliest adopters of XuanTie. I can confidently say that we are a firm supporter within the industry, working with XuanTie on RISC-V chips. Our considerations were based on several points: First, our company's foundation is in wide-area IoT connectivity chips, such as 5G, cellular, AIoT, and now satellite communications, which are our main business. These connectivity chips cover many industry clients, requiring very high reliability. In this context, price is one factor, but reliability is more important. Furthermore, many industries are facing digitalization, now referred to as Physical AI. During this process, we face the demand for localization. Therefore, RISC-V quickly entered our development. Moreover, RISC-V is constantly evolving with the development of the chip industry and customer needs, such as rapid scalability. When we raise an issue, it's addressed promptly. So, over the past four years, we have witnessed firsthand the transformation from an initial idea to nearly 100 million units shipped this year. Our products are not only sold in China but also in Europe and many parts of the United States, becoming global products. In terms of the ecosystem, the implementation of artificial intelligence requires connectivity, especially constant connectivity, which serves as a crucial foundation. This is why the country is heavily promoting satellite communications. Even AT&T in the US recently invested over $100 million in satellite communication infrastructure construction. Imagine driving a smart car and suddenly losing control in a remote area; you wouldn't be able to drive. Therefore, constant connectivity is extremely important, making both satellite and cellular communication vital. Second, all AI is being moved to the cloud because it's not only uneconomical but also involves numerous deployment challenges. Terminal-side AI is undoubtedly a very important testing ground for RISC-V. Therefore, in terminal-side AI, from basic small model applications, due to their significant power consumption, to medium computing power of several Tflops, and even future applications like smart glasses (which will undoubtedly require running large models), we need to incorporate excellent energy efficiency terminal computing power, combined with connectivity and some AI processing capabilities. This is crucial, scaling from low to high computing power, and then to edge AI. Simultaneously, as mentioned regarding Physical AI, a critical aspect is industry application. In the future, many industries will undergo transformation, much like electricity replacing steam a century ago. Each industry will deploy AI, facing diverse needs. It cannot be just connectivity or just computing power; it must integrate with various sensors and security features. Deep customization is essential to help these industries rapidly adopt Physical AI, which is what our company is focused on. Therefore, we are advancing connectivity, edge AI, and Physical AI in these three areas. This endeavor requires individual effort, making open source and ecosystem incredibly important. Thus, we have been collaborating with leading companies like DAMO Academy. I believe that for many industries we encounter, RISC-V is no longer a question but an inevitability due to its numerous advantages, not only in chip competition but also in international competition and industrial implementation. We see significant advantages, and we are involved in satellite communications for the future. I also believe that in the future, beyond CPU + NPU combined with various models, RISC-V will have vast exploration and growth potential. This is our philosophy. **36Kr Tech:** In terms of future manufacturing, how are you planning the integration of CPUs with NPUs or AI accelerators? **Jiang Tao:** I am from Shanghai Sophon Technologies. This company actually focuses on high-power power supplies. Power supplies today are different from before. Whether it's terminal or server-side computing power, it's growing significantly, leading to higher demands on power management. What was previously a simple power management chip, primarily analog processing, has now evolved. We develop power supply chips that are actually very complex. Without the open-source ecosystem kernel supported by DAMO Academy, we couldn't achieve this, or it would take us a very long time to transition from a pure power company to a digitally integrated one. This is because current power chips, I recall from seven or eight years ago, were very small; now, they are much larger and incorporate substantial digital components. In essence, this area represents a significant future investment for us. Moving forward, our secondary and tertiary growth will focus on ultra-high power, higher value-added products for servers and automotive OPC. To give you a number, through our collaboration with DAMO Academy over these years, our shipment volume has exceeded 100 million units. These are used for relatively complex power chips, including high-end domestic power battery packs, and some of our products are even integrated into domestic large aircraft. Additionally, we are engaged in synchronized development with leading domestic computing power enterprises, companies that are well-known. This necessitates that, in addition to our original digital chip foundation, we address higher demands for computing power and more complex power requirements. Thus, our collaboration with DAMO Academy is crucial, and we believe our needs for certain kernels will continue to increase. **Meng Jianyì:** I believe that if we reach 10 billion units, meaning we have 100 such companies, it should be quite fast. Regarding our plans for NPUs in AI, as you know, NPUs were a technology type used in many terminal chips in earlier stages. However, this technology type faces certain challenges in its technical route today, primarily because it's difficult to form an ecosystem. This means that if an NPU is maintained by a specific company and continuously upgraded, it can only be done by that company. But today, we have released two AI acceleration engines, which differ somewhat from past NPUs because they are built within the broader RISC-V ecosystem. For instance, our RVV is already a standardized RISC-V component. This implies that once we have this core, all RVV programs can run on it, allowing us to build an AI ecosystem, which traditional NPUs cannot achieve. We are also currently working on AME, a standard that has not yet been ratified, but we do have our proprietary Matrix standard, which has already been released. However, this is not an issue; as the standard is promoted, we can transition to it later. Therefore, to answer Mr. Zhang's question, building NPU-like devices today will be based on the standardized interface at the RISC-V level. In the future, as we accumulate experience and iterate generation after generation, our NPUs will become increasingly effective. **36Kr Tech:** Is there a significant head effect in the RISC-V industry? **Meng Jianyì:** At its current stage, RISC-V requires investment. Today, as seen from DAMO Academy's efforts over four years, we have gained a large number of clients. However, over these four years, we have made very substantial R&D investments. Therefore, smaller companies may need to immediately address their immediate survival needs. For us at Alibaba today, we are looking at the value the entire RISC-V ecosystem will bring to us in the next five to ten years. Therefore, in our current layout, on the IP side, we have almost been paving the way for everyone. We were very early in China's RISC-V development. We launched products early on, then helped others with customization, and today we are launching new products to assist our clients in their own customization. This is an ongoing evolution. This process requires patience and perseverance. Therefore, today, both in China and globally, there is a need for companies like ours to invest heavily. DAMO Academy is making substantial investments, which is the current situation. Hence, the head effect is very important. **36Kr Tech:** The newly released chip has achieved coordination and unification of generality and customization. What conditions made this possible? **Meng Jianyì:** As I mentioned during the C950 launch, it offers excellent general-purpose performance, which we measure using metrics like SPECint. However, RISC-V goes beyond this. Therefore, as I stated earlier, in our practical experience, we have already been making extensions and pushing the boundaries of RISC-V performance. I provided several examples earlier. Beyond SPECint for general-purpose computing, I added several others related to typical cloud computing scenarios, including databases and three other benchmarks. The performance level we have achieved today is the highest attainable and demonstrable in the general-purpose domain, placing us in the top tier. On top of this, I also presented another figure showing a 30% improvement in storage and network performance through instruction set extensions and structural optimizations. These instructions are currently being proposed as standards, and we are willing to standardize them in the future, which could then become a general-purpose feature. Therefore, today, I want to present that DAMO Academy, based on RISC-V, can create products that outperform general-purpose products in specific market segments. This is what we are doing now. However, we also hope to share this capability with everyone, enabling you to create more competitive products. This is how we differentiate RISC-V from previous approaches, and we are demonstrating this through practical actions. **Jiang Tao:** Let me briefly elaborate on the current situation regarding power supplies. This is not limited to Shanghai Sophon; we are among many participants. Currently, apart from consumer electronics, especially mobile phones, where only a few manufacturers produce directly, we are involved in power chips for phone screens and even memory power chips. The most complex PMIC chips we develop have numerous LDO and DC-DC channels, such as 16 channels plus 32 channels, making them extremely intricate. As I mentioned, we also have charging chips for automotive OPC, which are also very complex, featuring multiple channels without a unified core. Without the open-source support of the RISC-V kernel, we would not be able to achieve this, or it would take us many years. Currently, Sophon is involved in several major categories, including DrMOS for servers, and we are even developing GaN in-house, which will be integrated into ICs. For these chips, especially GaN, several domestic competitors are also working on this, while overseas suppliers do not yet have comparable offerings. Why is the domestic market dominant? Because there are too many categories of power supplies, from single-category power supplies to complex ones, and PMIC categories, with numerous application scenarios that we must individually tackle and master. **36Kr Tech:** Regarding the issue of fragmentation and unification, if unified, it lacks vitality, while customization fosters creativity. How is this balance being struck? **Lu Dai:** I believe RISC-V's greatest advantage lies in its ability to allow for highly flexible customization while maintaining a set of standards. Companies can pursue different technical paths based on their specific needs. The RISC-V architecture itself is divided into "mandatory extensions" and "optional extensions." When you develop optional extensions, you are essentially working on extensions that have not yet been officially approved. Beyond these, there is a third layer: "custom extensions" developed entirely independently by the enterprise. Whether these extensions eventually become standards depends on market adoption. If clients use them extensively and recognize their value, they may be upgraded to official standards. Therefore, some worry that incorporating these elements into the standard system might reduce innovation. However, the opposite is true – RISC-V standards themselves evolve from customization. If certain directions gain industry consensus, they can be directly incorporated into the main standards. If consensus hasn't formed yet and the technology is rapidly iterating, different approaches are permitted. For example, with our matrix extension, other routes exist in the market, and ultimately, the market will decide which approach is more widely accepted. Hence, I absolutely do not believe that standardization hinders innovation. On the contrary, this ability to continuously iterate standards through market screening within an open system is something only RISC-V can achieve at present. Meng Jianyì:\*\* Standards do not stagnate; they continuously evolve with market validation, eventually absorbing solutions truly accepted by the industry and integrating them into the mainstream. Consequently, RISC-V will become increasingly powerful, and this dynamic evolution is itself a form of innovation. Another layer of innovation lies in RISC-V requiring adherence to fundamental standards, while granting companies complete freedom to innovate beyond those standards. Therefore, at this juncture, we must refine the IP of the standard components to ensure smooth operation of operating systems and stable reliability of basic software libraries. Above this, we fully open up the space for users, rather than requiring them to completely rewrite the entire kernel. This is not only costly but also leads to a loss of ecosystem support. We believe the true path is: aspects required by the ecosystem must adhere to standards, while the space beyond the standards is precisely the innovative freedom RISC-V provides to the industry. In the future, when certain innovations gain industry consensus, they may become new standards, and the system will evolve once more. Through this cycle, RISC-V forms a system that is continuous, self-consistent, and vibrantly innovative. In my view, this is a unified and open innovation process. **36Kr Tech:** As a downstream partner of XuanTie, why did Allwinner choose XuanTie? **Huang Shaorui:** I understand this question this way: the primary reason is that we have observed XuanTie's long-term and continuous investment in the RISC-V direction. From our perspective as a terminal SOC company, we see far beyond just the IP layer. To effectively utilize and develop RISC-V, beyond the IP itself, we need software, toolchains, and the entire ecosystem. This latter part requires extremely significant investment. Throughout our years of collaboration, we have seen the XuanTie team's investment in this direction as both sustained and resolute. Second, Allwinner has a vast product portfolio covering various applications. We require some smaller solutions, while other scenarios demand larger ones, indicating a broad range of applications. The XuanTie product series is well-matched with Allwinner's product matrix, allowing us to find effective entry points. This is another key reason for choosing XuanTie. **36Kr Tech:** What is the greatest benefit of choosing XuanTie? **Huang Shaorui:** Allwinner has six product lines, and two of these currently utilize RISC-V IP. After integrating XuanTie's IP into these product lines, we can address specific customized needs through effective interaction with XuanTie, incorporating our scenario-specific requirements into our implementation solutions. Ultimately, these benefits are reflected not only in the IP itself but also in the architectural implementation capabilities of the entire IP delivery. This is also very important; it can be a standardized component, but its implementation is another matter. Through this combination, we can rapidly address certain pain points in our scenarios using XuanTie's IP. **Jiang Tao:** The reason we initially chose RISC-V is that we believe it presents an opportunity for a breakthrough for a new company like Sophon. Of course, for developing kernels, RISC-V can be considered a teenager, perhaps not yet a young adult. This teenager requires collaboration between users and developers to be nurtured forward. This is why we chose RISC-V. Furthermore, why we chose to collaborate with DAMO Academy is twofold: we recognize their investment and their leading position, and they are geographically close to us. Looking back at this decision, it has helped us acquire many clients, both in terms of shipment volume and expanding our customer base with leading enterprises. The results have been very beneficial, proving that our initial choice was correct. The benefits include products, clients, and lower costs. The cost is definitely highly competitive, especially in China's intensely competitive market, where price is always a primary consideration. Price does not conflict with competitiveness or customization. We aim to create higher value-added products in the general market, as RISC-V's modularity offers us great flexibility, thus reducing costs. **36Kr Tech:** Is the launch of this new chip strongly related to OpenCLAW? Meng Jianyì:\*\* It should be said that the AI wave is fair to everyone. It doesn't necessarily mean that our two products today will immediately drive it. I rather think that our products are undoubtedly designed for this purpose, but not specifically for "Lobster." "Lobster" is a phenomenon; tomorrow it might become a rhinoceros, or the day after, something else. I think these things will change. However, there is one point we firmly believe in: Agentic AI will undoubtedly progress. Therefore, this requires strengthening CPUs and rethinking how CPUs and GPUs should cooperate, what platforms AI will ultimately run on, and how to optimize the entire system. These are questions we need to answer anew today. Previously, there was no need to answer them; with GPUs as the primary focus, other options were almost nonexistent. Today, this trend has shifted, and it's returning. Personally, I have firm confidence that it will return. Why? Because in this world, we have a vast amount of interaction that requires general-purpose computing, not just AI accelerated computing. Accelerated computing is excellent for specific tasks, but general-purpose computing needs to make a comeback. Therefore, the bottleneck in general-purpose computing today is certainly being recognized. The core issue is how everyone will approach it in the future. So, I believe it's not just a "Lobster" phenomenon, but the general direction is certainly moving this way. Imagine if today you had truly excellent AI supporting your work, and upon returning, the article was already written. Wouldn't that be wonderful? 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