ASML (Minutes): Even if tariffs are implemented, it should not be the main party to bear the burden.

ASML (ASML) released its Q1 2025 earnings report (as of March 2025) during the US pre-market session on April 16, 2025, Beijing time:

Below are the Minutes of ASML's Q1 2025 earnings call. For a Quick Interpretation of the earnings, please refer to ASML: Order Decline "Raises Alarm," Will Tariffs Deal Another Blow? - LongPort

I. $ASML(ASML.US) Key Earnings Highlights

1. Q1 Performance

① Revenue: Total Q1 revenue reached €7.7 billion, in line with company guidance. Lithography system revenue amounted to €5.7 billion, with EUV sales at €3.2 billion and non-EUV sales at €2.5 billion. Logic chips accounted for 58%, while memory chips made up 42%. Equipment services revenue was €2 billion.

② Profits: Gross margin for the quarter was 54%, exceeding guidance, driven by installed EUV systems meeting customer productivity targets, favorable EUV product mix, and higher ASP from advanced configurations. R&D expenses were €1.161 billion, while SG&A expenses were €281 million, both in line with guidance. Net profit was €2.4 billion, representing 30.4% of total revenue, with EPS at €6.

③ Cash Flow: After strong free cash flow in Q4, Q1 free cash flow was -€475 million due to changes in customer payments/prepayments and ongoing fixed-asset investments for future capacity. Cash, equivalents, and short-term investments totaled €9.1 billion at quarter-end.

④ Shareholder Returns: In Q1 2025, ASML paid its third interim dividend for 2024 at €1.52 per share. Total 2024 dividends reached €6.40 per share. The company repurchased ~€2.7 billion worth of shares this quarter.

2. Guidance

① Revenue Guidance: 2025 revenue is projected between €30-35 billion, with 2026 being a growth year.

② 25Q2 Guidance: Total revenue expected between €7.2-7.7 billion; installed base management revenue ~€2 billion; gross margin forecast at 50%-53% (wider range due to tariff uncertainties); R&D expenses ~€1.1 billion; SG&A expenses ~€300 million.

③ Gross Margin: H2 margins expected below H1, but full-year margin still projected at 51%-53%, accounting for tariff uncertainties.

3. Market Trends

① AI growth remains a key industry driver. If strong AI demand aligns with customer capacity expansion, performance may hit guidance 上限; otherwise, it could reach 下限.

② Compared to 2024, logic chip revenue grows with advanced node adoption; memory chip revenue stays robust; installed base management revenue rises from larger equipment base, improved services, EUV contributions, and upgrade business.

II. Detailed ASML Earnings Call Content

2.1 Executive Key Messages

1. Technology Progress:

a. Low-NA Platform (e.g., NXE:3800E): Began upgrades to final 220 wafers/hour configuration this quarter, with rollout continuing through year-end; newly delivered systems meet full specs with maturity enabling mass production; multiple logic/memory clients advancing nodes with productivity gains that enable joint cost reductions, creating more single-patterning EUV opportunities (especially for DRAM).

b. High-NA Platform (e.g., EXE:5000/5200): Clients showcased milestones at February SPIA conference, demonstrating key performance and maturity advantages like process simplification, cost reduction, and cycle time compression (accelerating industry transition from low-NA to high-NA). Intel exposed >30k wafers/quarter with major step reductions; Samsung achieved 60% cycle time improvement in one test. Final EXE:5000 delivered in Q1 to three clients; EXE:5200 deliveries begin Q2. High-NA adoption has three phases: Current Phase 1 involves R&D facility integration and joint capability exploration; Phase 2 (2026-2027) will test pre-production readiness on 1-2 layers; Phase 3 deploys high-NA for critical layers at leading nodes.

2. Market Dynamics: Semiconductor growth remains AI-driven, though global uncertainty rises from tariff discussions. Client dialogues suggest 2025-2026 as growth years, with end-market trends favoring advanced logic and DRAM.

3. Long-Term Outlook: 2030 revenue projected at €44-60 billion with 56%-60% gross margins.

2.2 Q&A

Q: Would flexible pricing accelerate high-NA adoption?

A: Single-patterning inherently benefits clients over multi-patterning via simplicity and cost. While we incentivize adoption, maturity—not tool price—is the gating factor. High-NA’s current maturity surpasses low-NA’s at this stage. Premature discounts would backfire if tools prove unreliable.

Q: Timing for single-patterning EUV adoption in DRAM?

A: Each new node (e.g., 3800E) enabling cost-optimized technology creates adoption opportunities. This long-term effort shows progress—3800E is 30% faster than 3600D.

Q: Order backlog needed to meet 2025-2026 growth?

A: We avoid growth quantification. Current backlog includes post-2025 commitments, but new orders remain essential. Next quarter will clarify momentum, though lumpy orders obscure precise signals.

Q: China revenue now slightly above 25% vs. prior ~20%?

A: The increase reflects stronger DUV demand. China’s backlog share remains 20%-25%.

Q: Tariff discussions with clients—any delivery timing changes?

A: No material shifts post-announcement. Constraints like fab space limit speculative early deliveries.

Q: Status of leftover 3600 inventory? Can it be upgraded to near-3800 specs?

A: No concerns here.

Q: Low-NA EUV average price ~€227M at 55%+ gross margin—any one-time impacts?

A: Calculation is correct. Future modeling assumes ~€220M average. We don’t disclose product-level margins, though low-NA currently exceeds corporate average.

Q: China’s EUV tool progress—scalability/reliability?

A: No breakthroughs. Even with research demonstrations, commercial EUV remains years away for China.

Q: AI inference demand impact on long-term outlook?

A: Clients confirm strong logic/memory demand. As AI shifts focus from training to inference, this segment’s growth will expand.

Q: Full-year tariff impact on margins?

A: Too dynamic to quantify. We aim to minimize chain-wide impacts, with next-in-line bearing primary burdens.

Q: Geographic fab diversification’s effect on WFE?

A: Dispersion may increase net capacity needs despite efficiency losses—a mixed long-term picture.

Q: EXE:5000 to EXE:5200 milestones?

A: Three phases: R&D validation (current), limited production testing (2026-2027), full deployment (2027-2028).

Q: High-NA adoption sequence—logic vs. DRAM?

A: Hard to separate—both have strong incentives once mature.

Q: China’s top-4 chipmakers’ revenue share?

A: Declining over time as long-tail customers emerge, though large firms still dominate.

Q: Can China produce 28nm chips with NXE:1950i multi-patterning?

A: Absolutely—historically achieved by others.

Q: Backlog pricing terms (tariff allocation)?

A: Varies by contract, with fair chain-wide cost-sharing.

Q: EXE:5200 production timing?

A: 2025 revenue recognition expected for 5 systems (including 5200s).

Q: 2026-2027 AI-driven outlook?

A: Strong investment momentum confirmed by clients, though 2027 remains uncertain.

Q: Single-patterning EUV timeline?

A: Gradual transition as cost parity improves, with DRAM showing earliest shifts.

Q: Tariff impact on orders?

A: Order lumpiness masks any clear signals.

Q: 2025 target midpoint progress?

A: EUV at midpoint; DUV ~90% there.

Q: US tariff contradictions?

A: Industry exemptions exist, but broader ecosystem review continues.

Q: High-NA backlog coverage?

A: Double-digit orders cover Phases 1-2; Phase 3 orders await mass-production confirmation.

Q: Phase 3 high-NA order timing?

A: Minimal 2025 activity—most still in Phase 1.

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Disclosures: Dolphin Research Disclaimer