Facing strong competition from Samsung and Intel, TSMC's leading position is facing unprecedented challenges. Intel even declared the slogan &#34;reclaiming the world's chip manufacturing crown&#34;. Will they be surpassed or continue to sit firmly on the throne?
Recently, TSMC unveiled a series of new chip technologies at a North American technology forum, once again taking a commanding lead. The release of these new technologies is a strong response to the challenges posed by Samsung and Intel. After the event, many analysts believe that Intel's optimism about reclaiming the chip manufacturing crown is too optimistic.
<h2>1. Introducing 3D Optical Engine to Layout Next-Generation Communication Technology</h2>
TSMC is preparing to use chip-making methods to create optical modules, saving power and space.
The current communication networks use optical module technology that mainly assembles various components together (see the figure below).
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/2585c8f0-c5fd-4a5c-8410-ad68803f95ad.png?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/2585c8f0-c5fd-4a5c-8410-ad68803f95ad.png"/>
This integrated approach, as transmission speeds increase, leads to high power consumption issues.
To address this problem, TSMC has introduced a new optical module product. In simple terms, the technology used to make chips is now being applied to the production of optical modules. This method significantly reduces the size of optical modules, optimizing material costs, chip costs, and packaging costs.
This is a new type of optical module technology and is recognized by the industry as the next generation of communication technology.
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/57c684b2-d3dc-4d0e-915f-b22f631a7cf6.png?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/57c684b2-d3dc-4d0e-915f-b22f631a7cf6.png"/>
(TSMC 1.6T Optical Engine Product Image)
However, TSMC is not the only player in the silicon photonics field. Other manufacturers such as Global Foundries, IMEC, and PowerJazz have also made early layouts. Since silicon photonics chips are not advanced processes, usually between 45nm and 130nm, domestic silicon photonics design companies mostly rely on Global Foundries, IMEC, PowerJazz, and other manufacturers for OEM production.
Compared to its peers, TSMC entered the silicon photonics market relatively late but is still ahead of Intel and Samsung. Additionally, at this conference, TSMC revealed its ambitious optical engine strategy, with a yearly iteration plan: introducing the 1.6T pluggable optical engine in 2025 and the 6.4T optical engine in 2026.
Considering TSMC's absolute position in the chip manufacturing field and the ambitious product strategy the company has set, in the future silicon photonics market, TSMC will be a force to be reckoned with and may capture market share from companies already developing in this field.
<h2>2. Backside Power Supply to Boost High-Performance Chip Demand</h2>
Using a new power supply method to improve chip spatial utilization.
Regarding chip power supply methods, the current mainstream practice in the market is to deploy the power supply on the front of the chip, which leads to power supply occupying chip space
TSMC's newly introduced backside power supply technology solves this issue.
In addition to TSMC, IMEC and Intel are also actively researching backside power supply technology. Compared to the three, IMEC has the lowest technical cost but inferior performance to TSMC; TSMC has the highest technical cost but the best performance. Overall, TSMC has the upper hand in backside power supply technology.
Overall, TSMC's innovative backside power supply solution can improve chip performance, power efficiency, and area utilization. It is expected to be widely used in future mobile devices and data center chips.
<h2>3. Beyond 3D packaging, a new choice - &#34;wafer-level system&#34;</h2>
By interconnecting chips on the wafer, data centers with no spatial limitations can achieve faster interconnection speeds.
As the number of transistors on chips increases, the market's demand for chip integration is also rising. Especially for terminals such as phones/computers, where chips cannot be large and must be compact, 3D packaging (vertical stacked chips) is mainly used for integration.
However, for scenarios like data centers where the chip area requirement is not very high, TSMC has introduced a new chip integration solution - &#34;wafer-level system&#34;.
This technology directly interconnects multiple chips on the wafer, mainly expanding the chip system horizontally (see the figure below), with the expected post-packaging size reaching 12x12cm.
TSMC has already released many products using this technology. For example, NVIDIA's B100 GPU launched this year consists of two Blackwell small chips forming a B100 chip; Cerebras' &#34;big chip&#34; connects 900,000 cores on the same wafer.
In wafer-level interconnection, TSMC is far ahead of its two major competitors, Intel and Samsung.
Overall, although TSMC's leading position is being challenged, it still remains the dominant player in the wafer field. Intel's big talk may not be so easy to achieve

159813

SOXS

TSMC introduces new chip technology, once again solidifying its leading position in wafer manufacturing

TSMC releases three new technologies in one go, once again challenging Intel?