According to the company and industry sources, Samsung Electronics is about to launch a three-dimensional (3D) packaging service for High Bandwidth Memory (HBM), which is expected to be used in the sixth-generation AI chip HBM4 to be launched in 2025.
On June 20, the world's largest memory chip manufacturer unveiled its latest chip packaging technology and service roadmap at the 2024 Samsung Foundry Forum in San Jose, California. This is the first time Samsung has publicly released its 3D packaging technology for HBM chips in the field of technology. Currently, HBM chips are mainly packaged using 2.5D technology.
Two weeks ago, Nvidia co-founder and CEO Jensen Huang announced the new generation architecture of its AI platform Rubin during a speech in Taiwan. HBM4 is unlikely to be embedded in Nvidia's new Rubin GPU models, which are expected to be launched in 2026.
Samsung's latest packaging technology will vertically stack HBM chips on top of GPUs to further accelerate data learning and inference processing, a technology seen as a game-changer in the rapidly growing AI chip market.
Currently, HBM chips are horizontally connected to GPUs through a silicon interposer in the 2.5D packaging technology. In contrast, 3D packaging does not require a silicon interposer or a thin substrate between chips to allow them to communicate and work together. Samsung refers to its new packaging technology as SAINT-D, which stands for Samsung Advanced Interconnection Technology-D.
It is reported that the Korean company provides turnkey 3D HBM packaging.
To achieve this, its advanced packaging team will vertically interconnect the HBM chips produced by its memory business unit with the GPUs assembled by its foundry department for fabless companies.
A Samsung Electronics executive stated, &#34;3D packaging reduces power consumption and processing latency, improving the quality of semiconductor chip electrical signals.&#34; In 2027, Samsung plans to introduce integrated heterogeneous integration technology, integrating optical components that significantly increase semiconductor data transfer speeds into a unified AI accelerator package.
Data from Taiwan research firm TrendForce shows that with the increasing demand for low-power, high-performance chips, HBM is expected to increase from 21% of the DRAM market in 2024 to 30% in 2025. MGIResearch predicts that by 2032, the advanced packaging market, including 3D packaging, will grow to $80 billion, compared to $34.5 billion in 2023.
<h2>Samsung HBM 16H Requires Hybrid Bonding Technology</h2>
Samsung recently stated in a paper that manufacturing 16-stack High Bandwidth Memory (HBM) requires hybrid bonding.
The company presented a paper titled &#34;Research on D2W (Die-to-Wafer) Copper Bonding Technology for HBM Stacking&#34; at the 74th IEEE Electronic Components and Technology Conference held in Colorado last month, indicating that hybrid bonding for 16 stacks and above of HBM is necessary
Hybrid bonding is the next-generation packaging technology, where there are no bumps between the stacks when chips are vertically stacked using Through Silicon Via (TSV) or micro copper wires. They are directly stacked. Therefore, hybrid bonding is also known as direct bonding.
Compared to the currently used Thermal Compression (TC) bonding, more chips can be stacked at a lower height with improved heat dissipation efficiency.
Samsung stated in a paper that the lower height is the main reason for adopting hybrid bonding. In order to package 17 chips (one base chip and 16 core chips or stacks) within a size of 775 microns, the gaps between the chips must be reduced.
Samsung has used TC non-conductive films to stack chips up to its 12-stack HBM.
In addition to applying hybrid bonding, other methods to address this issue include making the core chips as thin as possible or reducing the bump spacing.
However, two methods other than hybrid bonding are considered to have reached their limits. An insider mentioned that controlling the thickness of core chips to below 30 microns is very challenging. Samsung also pointed out in their paper that there are limitations to using bump connections due to the volume of the bumps. The tech giant also noted that the bump shorting issue makes reducing the spacing difficult.
Samsung also shared their plans on how to manufacture HBM using hybrid bonding. Logic wafers undergo Chemical Mechanical Polishing (CMP) and plasma processes. The wafers are then rinsed with deionized water. The chips are then stacked. Core chips undergo chip separation process after CMP. Subsequent processes are similar to logic wafers. Plasma processes and rinsing are to activate the surface. This will form a hydroxide on the surface, bonding the particles together. Copper will also be bonded after an annealing process.
In April this year, Samsung used its subsidiary Semes' hybrid bonding equipment to manufacture HBM 16H samples. The tech giant stated that the chip operates normally. Apart from Semes, BESI and Hanwha Precision Machinery are also developing hybrid bonding equipment.
Samsung stated that they plan to manufacture HBM4 samples (primarily 16-layer stacks) in 2025 and start mass production in 2026.
<h2>Samsung Wins Nvidia's 2.5D Packaging Order</h2>
According to Korean media TheElec's report in April this year, Samsung has won Nvidia as a 2.5D packaging customer.
Sources mentioned that the company's Advanced Packaging (AVP) team will provide interposer and I-Cube 2.5D packaging to the GPU manufacturer.
The production of High Bandwidth Memory (HBM) and GPU wafers will be handled by other companies.
2.5D packaging places chip modules (CPU, GPU, I/O, HBM, and other modules) horizontally on the interposer.
TSMC refers to its 2.5D packaging technology as Chip-on-Wafer-on-Substrate (CoWoS), while Samsung calls its technology I-Cube.
Nvidia's A100 and H100 are manufactured using this packaging technology, as well as Intel's Gaudi
Samsung has been committed to protecting its 2.5D packaging service customers since last year.
The tech giant has proposed to allocate sufficient personnel to the AVP team for customers, while providing its own interposer wafer design.
Sources say Samsung will provide Nvidia with a 2.5D package with four HBM chips placed on it.
They added that the South Korean tech giant already has packaging technology for placing eight HBM chips.
At the same time, they also mentioned that installing 8 HBM chips on a 12-inch wafer requires 16 interposers, which will reduce production efficiency.
Therefore, when the number of HBM chips reaches 8, Samsung is developing panel-level packaging technology for the interposer.
Nvidia is likely to hand over orders to this South Korean tech giant due to increased demand for its AI chips, which means TSMC's CoWoS capacity may be insufficient.
This order may also help Samsung win HBM orders.
Source: Semiconductor Industry Observation, Original Title: &#34;Samsung to Launch 3D HBM Chip Packaging Service&#34;

SSNGY

Samsung Electronics is about to launch a three-dimensional packaging service for high-bandwidth memory (HBM) to accelerate data learning and inference processing, which will have a significant impact on the AI chip market. Samsung's latest packaging technology will vertically stack HBM chips on top of GPUs without the need for silicon interposers or thin substrates to communicate and collaborate. The company plans to introduce integrated heterogeneous integration technology in 2027, integrating optical components into AI accelerator packaging to improve semiconductor data transmission speeds. These new technologies are expected to reduce power consumption, increase processing speed, and change the competitive landscape of the AI chip market

Samsung to launch 3D HBM chip packaging services