Author: Zhang Yifan
Editor: Shen Siqi
Source: Hard AI
Taiwan Semiconductor has been very active recently, from raising prices for advanced processes to entering the &#34;square substrate&#34; market.
Recently, Morgan Stanley released a report on Taiwan Semiconductor, detailing the latest developments in CoWoS, PLP technology, and 3D SoIC.
<blockquote>
• CoWoS Packaging: Taiwan Semiconductor expects that by the end of 2026, the monthly CoWoS wafer capacity will reach approximately 60,000 pieces; more than double the previously disclosed 26,000-28,000 pieces per month by the end of 2024;
• Panel Level Packaging (PLP): This technology is related to the recent market focus on &#34;square substrates&#34;. Currently in the research and development stage, mass production will still take several years;
• 3D SoIC Packaging: Capacity is expected to increase starting from the second half of 2025, with the Rubin architecture possibly adopting 3D SoIC packaging technology.
</blockquote>
<h2>I. CoWoS Capacity Update</h2>
At a recent technical seminar, Taiwan Semiconductor stated that from 2022 to 2026, the capacity of CoWoS technology is expected to grow rapidly at a compound annual growth rate of over 60%. By the end of 2026, the monthly CoWoS wafer capacity will reach approximately 60,000 pieces.
Currently, Taiwan Semiconductor's monthly CoWoS capacity is about 15,000 pieces, and it is expected to increase to 26,000-28,000 pieces per month by the end of 2024.
In 2024, Taiwan Semiconductor plans to invest $28-32 billion, with approximately 10% allocated to advanced packaging technology.
Morgan Stanley analysts pointed out that strong packaging demand will be a major driver of rapid growth in Taiwan Semiconductor's non-wafer revenue in the coming years:
<blockquote>
• It is expected that from 2023 to 2026, the compound annual growth rate (CAGR) of Taiwan Semiconductor's non-wafer revenue will reach 31%;
• By 2023, non-wafer sales are expected to account for 13% of Taiwan Semiconductor's total revenue;
</blockquote>
1) CoWoS-L Packaging
Morgan Stanley noted that Taiwan Semiconductor is accelerating the expansion of its CoWoS technology, focusing on meeting the increasing demand for larger AI chips, especially with CoWoS-L technology.
CoWoS packaging technology is currently divided into three types: CoWoS-S, CoWoS-R, and CoWoS-L, with the main difference being the design of the intermediate layer, which is a critical layer connecting the chips.
With the increase in the size of AI chips, the CoWoS-S technology previously using a silicon intermediate layer faced yield issues.
To address this challenge, Taiwan Semiconductor introduced CoWoS-L technology, which uses LSI+RDL intermediate layers to effectively solve the yield issues of large chips.
Morgan Stanley expects that in the future, Taiwan Semiconductor's development in CoWoS technology will mainly focus on CoWoS-L to meet the increasing demand for larger AI chip areas
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/17fb08fa-0cb3-4282-a864-d15c6a5b52a4.png?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/17fb08fa-0cb3-4282-a864-d15c6a5b52a4.png"/>
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/a64c8a90-8eb2-44ed-871f-7f0f7e32b76a.png?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/a64c8a90-8eb2-44ed-871f-7f0f7e32b76a.png"/>
<h2>2. Panel Level Packaging (PLP) Technology</h2>
Morgan Stanley pointed out that Taiwan Semiconductor is researching Panel Level Packaging (PLP) technology, but large-scale production will still take several years.
PLP packaging is a packaging solution that rearranges chips on a larger rectangular panel (see left side of the image below).
Currently, Taiwan Semiconductor uses circular wafer substrates, leading to area wastage (see right side of the image below).
According to Nikkei Asia, due to the surge in computing demand brought by AI, Taiwan Semiconductor is exploring rectangular substrates measuring 510mm × 515mm.
The effective area of rectangular substrates is more than three times larger than circular wafers, which is expected to significantly enhance Taiwan Semiconductor's production capacity.
However, compared to circular substrates, rectangular substrates face issues such as uneven photoresist coating and easy fracturing.
Morgan Stanley pointed out that achieving large-scale production of PLP packaging technology will still require several years of technical breakthroughs.
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/1baa5de1-f1aa-4412-a450-79aacd066991.png?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/1baa5de1-f1aa-4412-a450-79aacd066991.png"/>
<h2>3. 3D SoIC Advanced Packaging</h2>
3D SoIC is an advanced packaging technology developed by Taiwan Semiconductor, focusing on achieving high-density vertical chip stacking (in contrast, CoWoS technology mainly focuses on horizontal stacking).
Morgan Stanley pointed out that currently, 3D SoIC technology is still relatively niche in the market, with only AMD adopting it in its Ryzen 3D and MI300 AI accelerators.
It is expected that starting from the second half of 2025, Taiwan Semiconductor will gradually increase the production capacity of 3D SoIC. By the end of 2025, the monthly production capacity of 3D SoIC is expected to reach approximately 12,000 to 14,000 wafers; by the end of 2026, it is expected to increase to 20,000 wafers per month.
In addition, Morgan Stanley speculates that NVIDIA's Rubin architecture and Apple's M5 processor may adopt 3D SoIC technology

It is expected that from 2023 to 2026, the compound annual growth rate (CAGR) of Taiwan Semiconductor's non-wafer revenue will reach 31%; Rubin architecture may adopt 3D SoIC packaging technology

Author: Zhang Yifan
Editor: Shen Siqi
Source: Hard AI
1. Key Descriptive Facts:
- TSMC has been active recently, raising prices for advanced processes and venturing into "panel-level packaging."
- Morgan Stanley released a report on TSMC, summarizing the latest developments in CoWos, PLP technology, and 3D SoIC.
2. Points and Supporting Logic:
- CoWos Packaging: TSMC expects the monthly CoWoS wafer capacity to reach about 60,000 pieces by the end of 2026, more than doubling the previously disclosed 26,000-28,000 pieces per month by the end of 2024.
- PLP Packaging: Related to the recent market focus on "panel-level packaging," this technology is currently in the R&D phase, with mass production still several years away.
- 3D SoIC Packaging: Capacity is expected to increase starting from the second half of 2025, with the Rubin architecture possibly adopting 3D SoIC packaging technology.
3. CoWoS Capacity Update:
- TSMC projects rapid growth in CoWoS technology capacity with a CAGR of over 60% from 2022 to 2026, reaching about 60,000 pieces per month by the end of 2026.
- Current CoWoS monthly capacity is around 15,000 pieces, expected to increase to 26,000-28,000 pieces per month by the end of 2024.
- TSMC plans to invest $28-32 billion in 2024, with about 10% allocated to advanced packaging technology.
- Morgan Stanley analysts highlight strong packaging demand as a key driver for TSMC's rapid growth in non-wafer revenue in the coming years:
  - Expected CAGR of 31% in non-wafer revenue from 2023 to 2026.
  - Non-wafer sales are projected to account for 13% of TSMC's total revenue by 2023.
4. CoWoS-L Packaging:
- TSMC is accelerating the expansion of its CoWoS technology, focusing on meeting the increasing demand for larger AI chips, especially with CoWoS-L technology.
- CoWoS packaging now includes CoWoS-S, CoWoS-R, and CoWoS-L, differing mainly in the design of the intermediate layer crucial for chip interconnection.
- With the rise in AI chip sizes, the previous CoWoS-S technology using silicon intermediate layers faced yield issues.
- To address this challenge, TSMC introduced CoWoS-L technology with LSI+RDL intermediate layers, effectively resolving yield problems for large chips.

How is Taiwan Semiconductor's advanced packaging progressing? | AI Dehydration