TSMC held an earnings conference this afternoon, announcing the performance of the company in 24Q2 and providing guidance for Q3. While performance is one aspect, it is a means to verify logic. More importantly, we need to see through appearances to understand the essence, and through clues to observe trends. Investing requires truly understanding industry trends. This kind of understanding must be forward-looking, otherwise how can one surpass the market? It must be grounded in first principles, knowing the facts and reasons behind them, otherwise how can one hold onto beliefs in the face of different opinions?
Regarding the minutes of the earnings conference, I saw that several brokerage electronic analysts had already issued them in the afternoon, very timely and excellent. Thumbs up to their diligence and quick response.
Regarding the breakdown of performance and business, the five ppt slides are shown below:
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Regarding future performance guidance, this slide is relatively more important, as follows:
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Based on the median values in the guidance, 24Q3 revenue is expected to continue to grow by 10% on a quarter-on-quarter basis (33% year-on-year), and gross margin is expected to continue to increase on a quarter-on-quarter basis. Achieving consecutive 10% quarter-on-quarter growth is quite strong, coupled with a steady increase in gross margin. This guidance should be satisfactory for investors
However, what I want to say is that we cannot simply look at financial data, as these are just outcomes. We should look for some clues, some clues that indicate industry trends. These industry trends are not only beneficial for your judgment on Taiwan Semiconductor's future, but also for understanding the global tech industry.
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TSMC starts wafer foundry 2.0
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What upgrades does 2.0 have over 1.0? It includes packaging, testing, mask making, and even memory manufacturing in the future roadmap. What does this mean for TSMC? It means that the market space expands from the original $115 billion to $250 billion, doubling the market space.
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The purpose of TSMC's move is implied to be a strong focus on packaging. For companies in the industry chain, especially those originally in packaging and testing, the giants will use their technological and financial advantages to compete.
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Why mention memory manufacturing? TSMC's ambition is not only to make logic chips in the future, but also to make memory chips, integrate logic and memory into one package, and complete the entire process in one stop.
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Why mention it now when it wasn't mentioned before? It wasn't mentioned before because customers didn't need it, but now it's mentioned in response to customer demand. This means that in the future, integration will become higher and higher. Not only will different types of chips be integrated together, but even components outside of chips will be integrated together. This integration is for better performance, not just cost reduction.
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This is not just TSMC's wishful thinking, but a response to customer needs for better performance. I think this is also the future of advanced wafer fabs in mainland China. Perhaps in the future, many electronic component companies will no longer have module factories as their direct customers, but advanced process wafer fabs.
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Cowos is in short supply, with annual doubling growth in the next two years, and a longer-term compound growth rate exceeding 60%.
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What is Cowos? Chip-On-Wafer-On-Substrate. Previously, Substrate, commonly known as an IC carrier board, was handed over by suppliers to semiconductor packaging companies to assemble into a finished chip. Now, TSMC has taken over this integration assembly work, and only TSMC can do it.
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There is a huge demand for Cowos from customers, so much so that there will be a shortage in 2023, 2024, and even in 2025, maybe easing in 2026. The premise for this easing is that TSMC's capacity will double in 2024, and then double again in 2025 based on 2024. After 2026, production will expand annually at a compound growth rate of 60%.
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Where does this demand come from? In 2024, which is the current year, customers have already placed orders and locked in capacity, so it is clear that NVIDIA, AMD, and Broadcom are the ones with high-performance computing (HPC) or AI high computing power-related demands. But in the future, it's not just HPC customers who have demand, it's customers including edge AI chip customers, such as smartphones.
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What are the differences in advanced packaging requirements between HPC and smartphones? HPC emphasizes data rate performance, so it values low latency. To minimize latency, the chip's internal wiring should not be too convoluted, resulting in limited die area optimization space. Therefore, the packaging aims to minimize re-routing (RDL). On the other hand, smartphones focus on thin thickness and small area (high pin density) after packaging, hence adopting advanced packaging like InFO-PoP (Package on Package + Integrated-FanOut).
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The A16 process is the industry's first backside contact conductive process that balances gate density and flexibility, making it most suitable for HPC with high requirements for both latency and power consumption.
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TSMC's process nodes include N28, N16, N14, N12, N10, N7, N5, N3, N2, and A16. Here, N stands for nano (10^-9 meters) and A stands for Angstrom (10^-10 meters), with 1N equaling 10A. Although there are many nodes, they can be categorized into groups, such as 16-12 and 10-7 (as shown in the pie chart split by process nodes in the above ppt). N5 and N3 are not in the same group, but their tool universality is over 90%.
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Why emphasize the universality of N5 and N3? Because 3nm is TSMC's most advanced process currently in production, and 5nm is the process with the largest revenue share (35%) for TSMC. Customers migrating to advanced process nodes are transitioning from the 5nm platform to the 3nm platform. Emphasizing their universality highlights the stability of gross profit margin during the migration process.
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In the past, under Moore's Law, process upgrades pursued cost reduction, what are process upgrades pursuing now? Moore's Law states that transistor density doubles every 18 months, meaning the area shrinks by half. A halved area implies half the material usage, resulting in cost reduction. The square root of 0.5 is approximately 0.7, so the previous process nodes 130nm, 90nm, 65nm, and 45nm form a geometric series with a common ratio of 0.7. However, by the time of 28nm, this cost reduction became ineffective, mainly because manufacturing costs outweighed material costs, becoming the major cost component. Therefore, 28nm is a turning point and the most cost-effective node. Under advanced processes, from N7 to N5 to N3 and N2 to A16, chip density certainly increases, leading to cost increases rather than reductions, but power consumption decreases. Even with A16, TSMC focuses on developing backside power supply processes to reduce power consumption. It is evident that power consumption is the most crucial indicator of future product competitiveness, even surpassing performance and cost. Therefore, companies that can provide value in terms of power consumption or heat dissipation in the future are valuable investment targets
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Why has TSMC clearly outperformed Samsung and Intel in recent years? Previously, Apple was still using Samsung for production, and Qualcomm even focused on Samsung, including NVIDIA. However, in recent years, they have continuously abandoned Samsung and chosen TSMC for production. In the end, it's still about meeting customer demands. Samsung couldn't meet them, while TSMC did. What demands couldn't be met? Power consumption! Why has the gap widened in the past two years? Because in these two years, the demand for semiconductors, especially power consumption requirements, has accelerated, rather than increasing linearly.
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It is expected that 2nm will achieve mass production in 2025, and it is also expected that within the first two years of the launch of 2nm, the number of new tape-outs (NTO) will exceed the number of new tape-outs for 3nm and 5nm in the first two years. It can be seen that the global demand for the highest-end, most advanced chips is accelerating.
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TSMC's long-term gross margin guidance is 53% or higher, with a strong emphasis on &#34;or higher.&#34;
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In 2021, the gross margin and long-term gross margin target were around 50%, and in recent years, the gross margin has gradually increased to 53%, with expectations for it to be &#34;or higher&#34; in the future.
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Why emphasize &#34;or higher&#34;? In the past, the gross margin of advanced packaging was much lower than the company's overall gross margin, but now it is starting to approach the company's overall gross margin. One reason is that economies of scale are starting to take effect, and another reason is the supply-demand imbalance and global scarcity.
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TSMC adopts strategic pricing for customers, rather than market-based pricing. In other words, TSMC could have priced higher, but to suppress competitors, price increases are relatively restrained. This is completely different from NVIDIA, whose pricing actually displeases customers. From this perspective, there is still considerable room for TSMC's gross margin to increase.
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TSMC not only has bargaining power downstream but also an increasing bargaining power upstream. This quarter's report shows that accounts receivable turnover days have decreased by 3 days to 28 days, a significant decrease in turnover days, indicating an increase in bargaining power with downstream customers. While the bargaining power with downstream customers is strengthening, the bargaining power with upstream suppliers is also increasing. In 24Q2, current liabilities increased by NT$23 billion, of which NT$16 billion (70%) were accounts payable.
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The capital expenditure budget for 2024 has narrowed to the upper range.
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During the 24Q1 earnings conference, the capital expenditure budget range for 2024 was given as $28-32 billion. This time, it is explicitly stated to be between $30-32 billion, specifically the upper range.
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70% to 80% of the capital budget will be used for advanced process technologies. Approximately 10% to 20% will be used for specialty processes, and about 10% will be used for advanced packaging, testing, mask manufacturing, and other aspects
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The company acknowledges that it made mistakes in overexpanding production capacity in 2021 and 2022, but it is disciplined and cautious about production capacity expansion in 2024 and beyond. This time, the demand is not only large but also real. For example, the globally popular AI, Taiwan Semiconductor also needs to queue to purchase NVIDIA's AI chips, and the use of AI indeed significantly improves production efficiency. AI not only greatly enhances efficiency in the semiconductor foundry industry but also in the medical industry, manufacturing, and autonomous driving. From this perspective, the demand for AI is essential, more practical than the previous AR/VR technologies. Therefore, investment opportunities in the AI-related industry chain are sustainable.
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In fact, it is not just these four clues, there are many small details that are crucial. For example, in terms of EDA tools, High NA lithography machines, advanced packaging incremental processes, equipment, and materials, it is impossible to comprehensively describe them all here. But these are all the best investment areas for the next 3-5 years.
Studying Taiwan Semiconductor is not only for investing in the company itself, perhaps the better investment opportunities lie in its related industry chain. At the same time, ensuring that in some major directions, not only should one not make mistakes but also make the right decisions.
Author: Liu Xiang, Source: Liu Xiang Technology Research, Slightly edited from the original

TSMC's financial report shows that the market space has doubled, with an expected annual growth rate doubling over the next two years. The long-term gross margin guidance is 53% or higher. TSMC has started wafer foundry 2.0, indicating that the market space has expanded from $115 billion to $250 billion. Industry trends indicate that TSMC will make significant investments in the packaging field

- TSMC held an earnings conference, disclosing 24Q2 results and guiding for Q3. The guidance indicates a 10% QoQ revenue growth (33% YoY) and a continuous gross margin improvement, reflecting strong performance and investor satisfaction.
- TSMC's shift to Wafer 2.0 signifies a market space expansion from $115B to $250B, focusing on advanced packaging and memory manufacturing, meeting evolving customer demands and enhancing industry competitiveness.
- Emphasizing on advanced technologies like A16 and N3, TSMC aims for a 53% or higher long-term gross margin, strategically pricing to maintain competitiveness and strengthen bargaining power across the supply chain.

Industry trends indicated by TSMC's financial report