Against the backdrop of the slowing Moore's Law, the semiconductor industry is investing more resources in advanced packaging. Currently, mainstream packaging technologies use silicon wafers. However, with the continuous growth in chip size and chip integration, glass materials are receiving more attention.
Given that glass may offer better cost-effectiveness, the application of glass in advanced packaging is gradually gaining traction. In its latest report this week, Morgan Stanley analyzed the potential, advantages, challenges, and market prospects of glass in the semiconductor industry.
Firstly, in terms of advantages and disadvantages, Morgan Stanley pointed out:
<blockquote>
Advantages: In addition to the cost advantage brought by larger panel sizes, glass can provide better electrical performance to reduce signal attenuation, higher resistivity to reduce crosstalk, reduce warping issues, and better mechanical strength to resist deformation during manufacturing. According to research firm Yole, fan-out panel-level packaging (FOPLP) can save 20-30% in costs compared to fan-out wafer-level packaging (FOWLP).
Disadvantages: Before being more widely adopted in high-performance computing chips, several challenges need to be addressed, such as improving line width/spacing, chip displacement, lower thermal conductivity, the tendency for small cracks to develop into major defects, and lower adoption rates in its ecosystem.
</blockquote>
Morgan Stanley further stated that glass has high potential in various advanced packaging applications, with the market space expected to grow at a compound annual growth rate of 37%. However, the supply chain will need several years to optimize solutions.
<blockquote>
We estimate that the fan-out panel-level packaging market will grow at a compound annual growth rate of 37%, reaching $252 million by 2028. Other applications of glass (interposer and substrate) may have more room for growth in the medium to long term. Supply chain players such as Intel, TSMC, and Micron are paying attention to this market, and significant commercial contributions may take several years to materialize, which could continue to be a focus of the market.
</blockquote>
<h2>Advantages and Disadvantages of Glass Substrates</h2>
Specifically, Morgan Stanley stated that the application of glass in packaging is similar to silicon wafers. Glass panels can be used as carriers in the packaging process to provide support, as interposers to provide interconnections between chips and substrates, and finally, glass can also be used in the core of the substrate.
<blockquote>
<ol>
<li>
Carrier: Glass plates can serve as temporary carriers to support chips and redistribution layers (RDL).
</li>
<li>
Interposer: Through glass through vias (TGVs) and redistribution layers, glass can act as an interposer, providing connections between chips and substrates.
</li>
<li>
Substrate Core: Glass can serve as the core of the substrate, replacing traditional organic cores, providing higher I/O density and better mechanical strength.
</li>
</ol>
</blockquote>
Morgan Stanley further detailed the advantages of glass panels:
<blockquote>
<ol>
<li>Large Size Advantage: Glass panels are larger than silicon wafers, providing better cost efficiency. For example, a 620mm x 750mm glass panel has an area of 465,000 square millimeters, which is 6.6 times that of a 12-inch silicon wafer, allowing more chips to be accommodated in a carrier or interposer. Additionally, glass panels are rectangular, while silicon interposers are circular, with the circular shape potentially leading to some unused areas at the wafer's edge
When the chip size increases, the efficiency of wafer area utilization may be smaller. According to Yole's data, the average carrier area utilization of 12-inch wafers is only 69%, lower than the 84% area utilization of 300mm x 300mm panels. Yole estimates that fan-out panel-level packaging can provide over 20% cost advantage compared to fan-out wafer-level packaging at similar yields.</li>
</ol>
</blockquote>
<blockquote>
<ol>
<li>Electrical Performance Improvement: Glass has a lower dielectric constant (2.5-3.2) than silicon wafers (3.9), which helps reduce signal loss and improve signal integrity. At the same time, the high resistivity of glass reduces current leakage and crosstalk.</li>
<li>Adjustable Coefficient of Thermal Expansion (CTE): The coefficient of thermal expansion (CTE) of glass can be adjusted through chemical formulations to alleviate warping issues caused by CTE mismatch between different materials, which may affect the functionality and performance of packaging.</li>
</ol>
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/e41d55bc-3a52-483c-971b-6c4bbb6c77c8.png?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/e41d55bc-3a52-483c-971b-6c4bbb6c77c8.png"/>
</blockquote>
However, glass panels also face some challenges in advanced packaging, such as chip displacement and warping, which may be exacerbated by larger sizes. Additionally, solutions are needed to mitigate its lower thermal conductivity and lower resistance to small cracks.
<blockquote>
<ol>
<li>
Chip Displacement: During advanced packaging processes, chips bonded to carriers, RDL, or interposer layers may be forced to move away from their designated positions, which can reduce packaging performance. Due to their larger area, glass panels are more prone to this issue compared to silicon wafers.
</li>
<li>
Interconnect Line Width and Spacing: Redistribution layers are used to connect chips (I/O) to other chips or substrates, and the line width and spacing are key performance indicators, determining the packaging's I/O density. With the continuous migration of process nodes, more and more I/Os will be packaged in a given area, so the line width and spacing on the redistribution layer also need to be finer.
</li>
<li>
Thermal Conductivity: Glass has a lower thermal conductivity (1.1-1.7 W/mK), which may limit its application in high-performance chips.
</li>
<li>
Risk of Cracking: Glass is fragile and may develop cracks during the manufacturing process, requiring optimized polymer layers or special TGV manufacturing techniques to mitigate.
</li>
<li>
Maturity of Ecosystem: The current supply chain is not yet mature and requires time to develop and increase production.
</li>
</ol>
</blockquote>
<h2>Market Potential of Glass in Advanced Packaging</h2>
However, Morgan Stanley believes that despite the challenges, glass still demonstrates significant advantages and market potential in advanced packaging, especially in terms of cost efficiency and electrical performance. With technology maturity and supply chain development, glass has broad application prospects in the semiconductor industry.
<blockquote>
**We estimate that the global fan-out panel-level packaging market reached $52 million in 2023 and may grow at a compound annual growth rate of 37% to reach $252 million in 2028. Particularly, there may be accelerated growth in 2026/2027 as the supply chain needs more time to optimize solutions for widespread adoption
**
In addition to fan-out panel-level packaging, glass can also find opportunities in the glass interposer or glass core substrate, so the overall market potential should be larger than the above estimates. For example, DNP plans to generate 5 billion yen (33 million USD) in revenue from glass core substrates in the 2027 fiscal year.
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/ae5d7b9e-b0da-4003-8fcf-fd4293c58b7e.png?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/ae5d7b9e-b0da-4003-8fcf-fd4293c58b7e.png"/>
</blockquote>
Overall, Morgan Stanley stated that we are still in the early stages of technical development, and the prospects for the next few years will largely depend on the development of the entire supply chain.
<blockquote>
We are seeing many participants from different supply chains paying attention to this market. Although the technology is still in its early stages, no one wants to be left behind in the technological transformation. Multiple players from various supply chains, including panel manufacturers, glass suppliers, semiconductor foundries/OSATs/IDMs, PCB/substrate manufacturers, and various equipment suppliers, have invested resources to varying degrees in this field, either to expand into new businesses or to avoid being replaced.
Among them, Intel has been one of the main participants driving glass core technology. In September 2023, after ten years of research, Intel introduced the industry's first glass core substrate for next-generation advanced packaging. It believes that the glass core substrate can achieve heterogeneous integration of multiple small chips, realizing system architecture within the package, which will help extend Moore's Law at the packaging level beyond 2030. Intel plans to commercialize this technology in the latter half of this century.
DNP is another company focusing on glass core substrates. It leverages its technology and expertise in semiconductor photomask printing processes and proprietary panel manufacturing processes to develop its glass core substrates, which were first launched in March 2023. DNP aims to generate 5 billion yen in revenue from this business in the 2027 fiscal year.
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/df527af8-ad3a-4041-9dd5-14276ad5e4a5.png?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/df527af8-ad3a-4041-9dd5-14276ad5e4a5.png"/>
</blockquote>

600586

601636

601865

06865

Morgan Stanley analysis pointed out that glass panels, as chip carriers or intermediate layers, can achieve higher cost efficiency, reduce signal attenuation, and minimize warping issues compared to silicon wafers. It is expected that the fan-out type panel-level packaging market will grow at a compound annual growth rate of 37%, reaching $252 million by 2028

- The semiconductor industry is increasingly investing in glass materials for advanced packaging due to their cost-effectiveness and superior electrical performance compared to silicon wafers.  
- Morgan Stanley's report highlights the potential growth of the fan-out panel-level packaging market, estimating a compound annual growth rate of 37%, reaching $252 million by 2028.  
- Despite challenges like chip displacement and lower thermal conductivity, the market for glass in semiconductor applications is expected to expand significantly as supply chains mature.

Glass - A great opportunity for advanced packaging