Recently, after Intel launched the A14 process, the two major wafer foundry giants officially entered the peak competition. From the current information, overall, they are engaged in fierce competition in architecture, EUV lithography, and transistor design.
First, let's look at TSMC. According to Dr. Yuh-Jier Mii, Executive Vice President and Co-CEO of the company, the current development direction is from FinFET to Nanosheet. In addition to these technologies, vertically stacked NFET and PFET devices (referred to as CFET) may also be candidates for achieving device miniaturization. Besides CFET, breakthroughs have also been made in channel materials, which can further achieve size reduction and lower power consumption. The above image summarizes these advancements.
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/9842330f-c5d4-42d0-b22f-d8e3d36668ab.jpeg?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/9842330f-c5d4-42d0-b22f-d8e3d36668ab.jpeg"/>
Dr. Mii reported that TSMC has been actively building silicon-based CFET devices to achieve higher levels of miniaturization. TSMC showcased its first CFET transistor with a gate pitch of 48 nanometers at the 2023 IEDM. This year at IEDM, TSMC demonstrated the smallest CFET inverter. The following image shows the balanced performance characteristics of the device at a voltage of up to 1.2V.
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/48d824e0-ce55-4950-b114-a678ba254d51.jpeg?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/48d824e0-ce55-4950-b114-a678ba254d51.jpeg"/>
He explained that this demonstration marks an important milestone in the development of CFET technology, which will help drive future technology expansion.
Dr. Mii reported that significant progress has also been made in the research of two-dimensional channel material transistors. TSMC showcased the electrical performance of a single-layer channel in a stacked nanosheet architecture similar to N2 technology for the first time. In addition, they developed an inverter using well-matched N-channel and P-channel devices, operating at a voltage of 1V. The following image summarizes this work.
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/8cc8a716-8b73-4b84-af3e-b4346646425c.jpeg?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/8cc8a716-8b73-4b84-af3e-b4346646425c.jpeg"/>
Looking ahead, TSMC also plans to continue developing new interconnect technologies to improve interconnect performance. For copper interconnects, we plan to adopt new via schemes to reduce via resistance and coupling capacitance. In addition, we are developing a new copper barrier layer to reduce copper line resistance.
In addition to copper, new metal materials with air gaps are currently being researched to further reduce resistance and coupling capacitance. Intercalated graphene is another promising new metal material that is expected to significantly reduce interconnect latency in the future. The following image summarizes this work.
<h2>Intel's Turbo Cell</h2>
Intel's upcoming 14A process node (scheduled for risk production in 2027) claims to reduce power consumption by up to 35%. Intel also showcased its new Turbo Cell technology, a customizable design approach aimed at delivering the highest CPU frequencies and enhancing performance in critical speed paths within GPUs.
The 14A and 14A-E nodes are the next generation following the 18A node. Intel stated that the performance-to-power ratio of the 14A node will improve by 15% to 20% compared to the 18A node, achievable through higher clock speeds or a 25% to 35% reduction in power consumption at the same performance level, depending on the chip's own tuning. This improvement is largely attributed to Intel's new direct contact back power delivery network, which the company has named PowerDirect.
Intel has also introduced other new features to enhance the node, such as a wider threshold voltage (Vt) range, allowing for a broader voltage/frequency curve.
The transistor density of the 14A node is also 1.3 times higher than that of the 18A node. Intel has improved its RibbonFET transistors for the 14A, now referred to as &#34;RibbonFET 2.&#34; Intel has not disclosed details about the next generation of RibbonFET, but its overall design increases transistor density and achieves faster transistor switching speeds by utilizing fully gate-enclosed four-layer stacked nanosheets (the above image shows a cross-section of nmos and pmos transistors).
Intel's new Turbo Cells feature is impressive but somewhat complex. Turbo Cells are versatile, but Intel specifically emphasizes that they will be used in the critical paths of CPUs and GPUs, commonly referred to as &#34;acceleration paths.&#34; There is a reason for this.
The timing paths within a processor refer to the routes that signals take through wires and logic gates during normal operation. However, the delays of these signals can disrupt the clock timing of the processor. The critical path is the path with the longest total delay.
Since processors operate based on clock signals, the slowest critical path determines the maximum frequency limit of the entire chip, thus becoming a bottleneck for overall performance (there are differences between clock domains, but the general principle remains the same). Chip designers typically use faster transistors in these areas of the chip, but this reduces transistor density and increases power consumption, as faster transistors leak more, consuming more power. The new Turbo Cells provide chip architects with finer tools to mitigate critical path issues.
Intel's new Turbo Cells feature is impressive but somewhat complex. Turbo Cells are versatile, but Intel specifically emphasizes that they will be used in the critical paths of CPUs and GPUs, commonly referred to as &#34;acceleration paths.&#34; There is a reason for this
The timing path within a processor refers to the path that signals take through wires and logic gates during normal operation. However, the delays of these signals can disrupt the clock timing of the processor. The critical path is the path with the longest total delay.
Since processors operate based on clock signals, the slowest critical path determines the maximum frequency limit of the entire chip, thus becoming a bottleneck for overall performance (there are differences between different clock domains, but the general principle is the same). Chip designers often use faster transistors in these areas of the chip, but this reduces transistor density and increases power consumption, as faster transistors leak more, consuming more power. The brand new Turbo Cells provide chip architects with finer tools to mitigate critical path issues.
Turbo Cells are designed to enhance performance by increasing the transistor drive current of short libraries, while maintaining high-density arrangements for optimal area efficiency when used to create dual-high libraries (two standard row heights).
The above figure shows four different arrangements of nmos and pmos nanowires/nanosheets (pink and green) with varying widths and configurations, optimized for drive current in different scenarios. The width of the nanowires can be adjusted and can also be merged individually to form very wide nanowires for maximum drive current output. The various options provide designers with a powerful toolkit for customized implementations.
Intel states that Turbo Cells can ultimately be used to mix faster, lower-power cells with energy-saving cells within the same design module, thereby creating an appropriate balance of power, performance, and area (PPA) for any given use case.
The critical path is the ultimate bottleneck; it can be viewed as the weakest link in a chain. Intel's brand new Turbo Cells aim to enhance the overall performance of processors by accelerating these paths without compromising like solving critical path issues would. We will have to wait until 2027 to see the final effects.
<h2>High NA EUV, how to choose?</h2>
As the core of next-generation manufacturing competition, when to use High NA EUV lithography machines is also a point of concern.
In the adoption of new elements in semiconductors, TSMC has been a pioneer for many years and often leads the trend. However, it now seems that the company will abandon the use of high numerical aperture EUV lithography equipment in its A14 process, opting instead for the more traditional 0.33 numerical aperture EUV technology. This news was revealed at a numerical aperture technology seminar, where TSMC Senior Vice President Kevin Zhang announced this development. It can be said with certainty that Intel's foundries and several DRAM manufacturers now have a technological advantage over TSMC.
&#34;TSMC will not use High NA EUV lithography technology to pattern the A14 chip, which is scheduled for production in 2028. From 2nm to A14, we do not need to use high NA, but we can continue to maintain similar complexity in processing steps. With each generation of technology, we strive to minimize the increase in the number of masks
&#34;This is crucial for providing economically efficient solutions,&#34; said Kevin Zhang of Taiwan Semiconductor.
According to reports, TSMC believes that the main reason high numerical aperture (NA) is irrelevant to the A14 process is that using the related lithography tools could cost the Taiwanese giant 2.5 times more than traditional EUV methods, which would ultimately significantly increase the production costs of the A14 node, making its application in consumer products difficult. The Taiwanese giant relies on chip design and capacity, but that does not mean the company will not adopt high numerical aperture EUV in future processes, as it plans to use it for the A14P node.
Another reason for the increased costs associated with High NA is that TSMC's A14 chip single-layer design requires multiple photomasks, and using the latest lithography tools would only raise costs without providing much benefit. Instead, by focusing on 0.33 NA EUV, TSMC can use multiple exposure techniques to maintain the same design complexity without the extremely high precision required by High NA EUV, ultimately reducing production costs.
However, TSMC later responded, stating, &#34;TSMC will carefully evaluate technological innovations such as new transistor structures and new tools, considering their maturity, cost, and benefits to customers before putting them into mass production. TSMC plans to first introduce high numerical aperture EUV lithography machines for research and development to develop the necessary infrastructure and patterning solutions required by customers, thereby driving innovation.&#34;
Intel explained the principles behind its High NA EUV strategy at this week's Intel Foundry Direct 2025 conference. Despite ongoing doubts about cost-effectiveness, Intel remains committed to using the new high NA EUV chip manufacturing equipment in its upcoming 14A process. However, Intel has not fully committed to using this new equipment in production, but it has an alternative production process using standard Low NA EUV as a backup for the 14A node.
Intel has installed a second high numerical aperture EUV lithography machine at its Oregon facility, and the company reports that the technology is progressing well. However, as it is still under development, this approximately $400 million ASML Twinscan NXE:5000 high numerical aperture EUV lithography machine has not yet been put into a production environment, so Intel will not take any risks.
Dr. Naga Chandrasekaran, Vice President of Intel's Foundry Technology and Manufacturing Execution, Chief Operating Officer, and General Manager, stated, &#34;First, Intel can still choose to adopt either Low NA or High NA solutions on our 14A technology, and its design rules are compatible, which will not affect customers, depending on the path we choose. Second, the performance of High NA EUV meets expectations, and we will launch it at the appropriate time.&#34;
&#34;We have mastered the data for 18A and 14A, which shows the yield parity between our low net short ratio solutions and high net short ratio solutions. Therefore, we will continue to make progress in technology and ensure that we have the right options to ensure that the solutions we deliver to customers have the lowest risk and the best returns in our decision-making,&#34; Naga explained.
Intel will only use High NA EUV on a few layers of the 14A node (the specific number is not clear), while other machines with different resolutions will be used for other layers. This means that the choice between the two machines will only affect certain parts of the manufacturing process, but Intel stated that using low NA EUV machines for triple patterning, instead of High NA EUV machines, can yield the same results.
Since both technologies are compatible with design rules, Intel's customers do not need to change their designs regardless of Intel's final decision on the manufacturing process (whether or not to adopt High NA EUV), which helps alleviate customer concerns about Intel adopting unproven production technologies.
Additionally, Intel claims that the yield rates for both production processes are the same, meaning that even if the development of high numerical aperture EUV encounters obstacles, or if Intel chooses not to deploy the technology for economic reasons, it will not severely impact the product's time to market. While multiple exposures typically reduce yield rates, Intel's claimed yield stability reflects advancements in modern multiple exposure technology, particularly in the area of lithography techniques.
Public discussions about high numerical aperture EUV have largely focused on costs. Industry insiders generally believe that the cost-effectiveness of high numerical aperture EUV is not as good as that of low numerical aperture EUV's multiple patterning technology, but there are still many technical hurdles to putting the machines into production. Most challenges focus on a series of complementary technologies required for achieving high numerical aperture EUV, such as photoresists, photomasks, and computational lithography techniques, which must be optimized for the new machines.
However, Intel has taken the lead in adopting ASML's machines to gain a competitive edge and has produced 30,000 wafers using high numerical aperture lithography technology during the development phase. As a representative explained later in the event, Intel has still achieved significant cost savings due to a reduction of about 40 process steps.
Finally, I want to talk about high numerical aperture EUV. Why are we doing this? The reason is simple: lower costs. The middle image shows the pattern generated by a single high numerical aperture EUV, with spacing comparable to what we need for 14A. The right side shows a very similar pattern generated using traditional methods, where we used three EUV exposures (triple patterning), going through about 40 process steps to generate that pattern.
&#34;So overall, we see a shorter and simpler process, which is the type of application we are using high numerical aperture (High-NA) for in 14A, reducing costs compared to multi-channel 0.33 NA EUV (low numerical aperture)
In addition, this provides options to reduce the number of metal layers and achieve additional performance enhancements.
Intel did not specify whether its comparison was based on full mask size printing. High numerical aperture (High-NA) machines can only print half a mask at a time, requiring two prints to create a processor the size of a full mask, relying on stitching to combine the two prints into a complete unit. In contrast, chips equal to or smaller than half a mask size can be printed in one go using high numerical aperture EUV machines. In comparison, low numerical aperture EUV machines can process a full mask size chip with just one print.
Intel faced numerous failures at the 10nm node, ultimately leading to its loss of the chip manufacturing lead over Taiwan Semiconductor, which Intel attributed to investing too much in new manufacturing technologies and processes simultaneously.
The decision to develop an alternative Low NA production process was made to prevent repeating past mistakes, and Intel has historically reduced the risks of other types of advancements by developing alternative solutions.
For example, the company developed an entirely new backside power delivery system at the 18A node, which is a first in the industry; at the same time, the company also developed gate-all-around (GAA) transistors, which is also a first in Intel's history. To ensure there were backup plans, the company adopted a more robust de-risking strategy for its 18A process, which included developing an internally tested process node without backside power delivery. However, as the development of GAA and backside power delivery progressed smoothly, Intel ultimately advanced the complete version of the 18A node.
Intel's competitor, Taiwan Semiconductor, has confirmed that it will not use high NA technology on its competing A14 node and has not disclosed when it will put the new high NA EUV equipment into mass production. Intel initially planned to use high NA technology in its 18A process, which was set to launch before the 14A node. Intel later changed these plans, stating that the development speed of this process node was unexpectedly fast, meaning the equipment could not be ready in time.
This article is sourced from: Semiconductor Industry Observation, original title: &#34;1.4nm, Peak Competition.&#34;
Risk Warning and Disclaimer
The market has risks, and investment should be cautious. This article does not constitute personal investment advice and does not take into account individual users' specific investment objectives, financial conditions, or needs. Users should consider whether any opinions, views, or conclusions in this article align with their specific circumstances. Investment based on this is at one's own risk

After Intel launched the A14 process, TSMC and Intel entered into fierce competition in the wafer manufacturing field. TSMC plans to transition from FinFET to Nanosheet and is actively developing CFET devices for miniaturization. At the 2023 IEDM, TSMC showcased 48-nanometer CFET transistors and their electrical performance, marking a technological advancement. In addition, TSMC is also researching new interconnect technologies and metal materials to reduce resistance and latency. Intel plans to launch the 14A process in 2027, claiming it will reduce power consumption

- Intel and TSMC are engaged in intense competition following Intel's launch of the A14 process, focusing on architecture, EUV lithography, and transistor design.  
- TSMC is advancing from FinFET to Nanosheet technology, while Intel's upcoming 14A process aims to reduce power consumption by up to 35% and improve performance metrics significantly.  
- TSMC has opted for traditional EUV technology for its A14 process, while Intel plans to utilize High NA EUV, highlighting differing strategies in semiconductor manufacturing.

1.4nm, the peak competition