This morning, the discussion about this new technology roadmap suddenly started... friends in the community are all exclaiming... there's too much to learn every day.
I researched it with a few friends and made some simple summaries. We are not technical personnel, just a few laymen analyzing the pictures, feel free to criticize any mistakes.
1/ Is this CoWoP roadmap reliable? Relatively reliable, the guy in the upper right corner, Anand Mannargudi, is a technician at NVIDIA and has been there for 12 years. Quoting contributors from internal technical PPTs is a very reliable detail.
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/531b1c15-7492-4f08-adf2-5980eb7fa11f.jpeg?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/531b1c15-7492-4f08-adf2-5980eb7fa11f.jpeg"/>
2/ How did this thing ferment? Some people saw it before the market opened on the weekend + Monday; however, today it fermented intensively, with a bunch of domestic sell-side firms releasing related interpretations, and there are many jokes, which we won't repeat here. But I searched for a long time overseas, and there's no related &#34;learning material&#34;; there are no overseas sell-side reports, and we also browsed IEEE for quite a while, but there aren't many relevant papers. A leading PCB company had small meetings last week and this afternoon, which should also be one of the triggers.
3/ How to understand this roadmap &#34;non-professionally&#34;? First, let's see what changes there are.
<ul>
<li>Compared to traditional COWOS (although called traditional, it is already a very advanced packaging technology), three things are gone: the entire &#34;packaging substrate + BGA balls&#34; has been cut off, and the &#34;bare chip module&#34; with a silicon interposer is directly soldered to the server motherboard.</li>
</ul>
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/d2d40421-aa2d-4911-88fb-66835cc34927.jpeg?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/d2d40421-aa2d-4911-88fb-66835cc34927.jpeg"/>
4/ Simply put, you can imagine the current AI chips as a combination of &#34;LEGO blocks.&#34; These blocks are built layer by layer with the following components.
<ul>
<li>
Chip (Die): The core computing unit, such as GPU cores and the adjacent HBM high-bandwidth memory.
</li>
<li>
Interposer: A high-precision silicon piece, like a &#34;adapter board,&#34; that allows the GPU and HBM chips to be placed closely side by side and communicate at high speed.
</li>
<li>
Package Substrate: A combination of the interposer and the chip, which needs to be installed onto a larger &#34;base,&#34; which is the packaging substrate. It is responsible for converting thousands of tiny signal points on the chip into larger solder balls for soldering onto the final circuit board.
</li>
<li>
Platform PCB: This is the common server motherboard that ultimately supports everything
COWOS structure (the left part of the above image) is already very advanced, and is the standard configuration for top AI chips (such as H100/H200) at present. However, its drawback is that there are too many levels, like building a tower, the more floors there are, the longer the path for signals and power to be transmitted from the ground to the top floor, resulting in greater loss and higher costs.
</li>
</ul>
5/ What is different about this COWOP?
The idea of CoWoP is very radical, and its core concept is: to remove all unnecessary intermediate levels.
It directly eliminates the expensive and heavy &#34;Package Substrate&#34; in the middle layer, and instead develops a highly technical &#34;Platform PCB&#34;, allowing the combination of &#34;chip + intermediary layer&#34; to be directly mounted on this enhanced motherboard.
In simple terms, CoWoP = CoWoS - Package Substrate.
This seemingly simple &#34;subtraction&#34; is a huge leap technically. This means that the motherboard (PCB) itself must possess some of the high-precision wiring capabilities that were previously provided by the package substrate.
6/ Some technical pros and cons; this part is a bit dry and can be read selectively.
What are the advantages?
Shorter interconnect paths - With one less layer of organic substrate, signals travel directly from the intermediary layer to the motherboard copper lines, resulting in lower NVLink / HBM signal attenuation and allowing for longer interconnect distances on the board.
Improved power integrity (PI); the VRM on the board can be closer to the GPU, with lower parasitic inductance and better instantaneous current response.
Better heat dissipation; by eliminating the package lid, it can directly use a cold plate or liquid cooling cold-plate, which is more important for GPUs over 1000 W.
Reduced thermal-mechanical mismatch; with the removal of the organic substrate that has the greatest difference in CTE (coefficient of thermal expansion), the risk of warping decreases.
Cost and capacity; organic substrates are currently the &#34;bottleneck&#34; in AI servers; removing it = fewer expensive and scarce processes.
What are the disadvantages?
Higher requirements for motherboard processes; line density, flatness, and tolerances must reach the level of the original packaging factory.
Difficulties in rework; once a GPU bare chip worth hundreds of thousands is soldered onto the motherboard, the yield/failure rate must be extremely low.
Complex packaging-system collaborative design; signal integrity, heat, and stress must be jointly simulated by the chip, intermediary layer, and PCB.
7/ What details need attention?
First, costs do not disappear, but are transferred. Although the expensive organic substrate (ABF Substrate) and traditional packaging steps are eliminated, costs will be transferred to the higher technical requirements for the &#34;Platform PCB&#34; and the more complex &#34;Die-on-Board&#34; assembly process; this has significant implications for the distribution of interests in the industry chain. Ordinary PCBs tend to become homogenized, while &#34;higher-level&#34; PCBs may bring about a huge competitive moat;
Costs may shift from packaging to PCB;
Second, it is a very aggressive route. NVIDIA's previous generation technology has often involved issues of capacity and yield, and this technological route may elevate these issues to another level. The ultimate goal is to reduce Total Cost of Ownership (TCO), including material costs, power consumption costs, and heat dissipation costs. Although direct costs in certain areas have disappeared, new costs and risks will emerge in other areas, NVIDIA's bet is that overall, the CoWoP solution will still outperform in performance and cost.
Third, it is quite likely that two technological paths will run in parallel, particularly with the mass production of the GR series; both routes may proceed concurrently (as indicated in the diagram); as an industry leader, NVIDIA retains the mature solution as a “safety net” to ensure that its product iterations and market supply are not interrupted by technological risks while the new technology is not yet 100% mature.
8/ For some industry players
For NVIDIA, “shifting the ‘performance bottleneck’ from chip processes to packaging/system-level interconnect; once this is truly accomplished, other manufacturers will continue to be left behind. Elevating competition from the ‘chip dimension’ to the ‘system dimension’, building a new moat through the complexity of system engineering.
For TSMC, “the silicon interposer area is larger, and TSMC's binding degree is higher”; in the CoWoP solution, TSMC's role may even shift from a “partial participant” in CoWoS to a “more core system integration consultant,” because it holds the most critical silicon interposer technology;
For ASICs, cloud giants may have enough capital and scale to replicate this path, but for AI chip startups, keeping up with such capital-intensive and ecosystem-heavy system-level innovations is almost impossible; NVIDIA has shifted the battlefield from “chip design” to “system integration.”
For HBM, “the inevitable choice of HBM4/5.” The number of stacking layers and I/O counts for HBM continues to increase, with increasingly stringent requirements for power supply and signal paths; traditional packaging methods will soon reach their physical limits; CoWoP was born to address the interconnect challenges of the next generation of memory.
9/ From a broader narrative perspective,
<ul>
<li>
NVIDIA is attempting to turn server motherboards into the “last packaging layer” for its GPU chips, thereby defining the entire AI computing hardware platform. NVIDIA is no longer just “selling chips”; it is defining a complete system-level platform of “chip + packaging + motherboard”;
</li>
<li>
If successful, it will trigger a value reconstruction and technological reshuffle across the entire semiconductor downstream industry chain (packaging, substrates, PCBs, server ODMs);
</li>
<li>
This is a necessary step towards the “Exascale” (100 quintillion) computing era. Without such packaging and integration technologies, the progress of chip processes alone can no longer meet the explosive growth demand for AI computing power
Today, another image was circulated in the community, which can be followed up on, regarding H20 and subsequent quantity forecasts.
</li>
</ul>
<img src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/118ee931-b1e8-4d14-8c32-bb55196540b6.jpeg?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/https://wpimg-wscn.awtmt.com/118ee931-b1e8-4d14-8c32-bb55196540b6.jpeg"/>
For other matters, feel free to continue the discussion in the community WeChat group;
The community and WeChat group continue to help everyone filter “important and narrative information” + “daily reviews” + “real-time discussions in the WeChat group”;
There are many institutional friends in the community WeChat group, welcome to come and sit. Recently, with various events in the market and various short essays... community members throw useful things into the WeChat group, feedback speed doubles, and debunking speed also doubles.
This article is sourced from: 180K, original title: “The CoWoP roadmap that went viral this morning (July 28)”
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This article discusses the emerging CoWoP technology roadmap, emphasizing its reliability, particularly mentioning the involvement of NVIDIA technician Anand Mannargudi. The article analyzes the dissemination process of this technology, pointing out the interpretations from domestic sellers and the impact of related conferences. The author explains the differences between CoWoP and traditional COWOS from a non-professional perspective, highlighting its simplified packaging process and comparing AI chips to Lego blocks, detailing the functions of each component

- The article discusses the new CoWoP technology roadmap, highlighting its potential reliability due to contributions from experienced Nvidia personnel.  
- It outlines the differences between CoWoP and traditional COWOS, emphasizing the removal of the packaging substrate to enhance performance and reduce costs.  
- The implications for the semiconductor industry are significant, as Nvidia aims to redefine the AI computing hardware platform, potentially reshaping the entire supply chain.

The viral CoWoP roadmap, PCB has a new story