CPO Harvest Battle, Fully Launched

If HBM has reshaped the internal bandwidth of GPUs, then CPO (Co-Packaged Optics) will reshape the external bandwidth of the entire AI data center. CPO technology significantly shortens the distance between optical transmission processing devices and semiconductor substrates, promising to increase data transmission speeds by ten times and reduce power consumption by half. It is not the next generation of optical modules, but the next generation of computing power infrastructure.

From an industry trend perspective, the progress of silicon photonics technology has clearly reached the "eve of explosion." This CPO industry chain diagram from Yole Group (as shown below) provides an exceptionally clear signal: from the upstream SOI/Epi-wafer, lasers, to the midstream PIC photonic chips, electronic chips, SerDes, advanced packaging, and down to the downstream cloud computing vendors, server manufacturers, and AI factories—over 150 companies have gathered to form a complete and diverse ecosystem.

In the past few months, we have seen the entire industry chain accelerate: foundries are crazily expanding silicon photonics capacity and acquiring silicon photonics specialty factories; chip giants are incorporating optical interconnects into their system roadmaps through mergers and acquisitions and establishing R&D centers; server manufacturers, cloud vendors, and AI factories are beginning to write "optical-electrical co-packaging" into the architecture of the next generation of data centers.

The battle for optical chips, especially the harvesting war around CPO, has fully commenced.

Foundry Manufacturers: Capacity and Technology Competition, the Arsenal of the CPO Era

Wafer foundries are the key drivers for silicon photonics to move from design blueprints to large-scale implementation. The logic of CPO is "optics closer, copper shorter," but the cost of implementation is "packaging more difficult, yield more sensitive, rework more expensive." Therefore, foundries are competing not just for a single SiPho process, but for a bundled delivery capability of PIC (photonic) + EIC (electronic) + heterogeneous 3D integration + usable design processes—whoever can turn it into a replicable manufacturing platform will gain the "arsenal" of the industry chain.

Samsung Enters Silicon Photonics

In the field of silicon photonics and CPO, TSMC and Intel have already positioned themselves in advance.

TSMC is the leader in the CPO market. This is thanks to one of its largest customers, NVIDIA, actively developing silicon photonics technology. At the developer conference "GTC 2025" in March, NVIDIA CEO Jensen Huang introduced a switching chip using silicon photonics technology and stated, "It will significantly reduce the costs for data center companies by eliminating the cost of transceivers and lowering power consumption." To further enhance its technical strength, TSMC is collaborating with Silicon Valley unicorns (startups valued at over $1 billion) such as Ayar Labs, Celestial AI, and Lightmatter Intel is the first company to commercialize silicon photonics technology. In 2016, it successfully applied silicon photonics technology to "transceivers," devices that allow remote servers to communicate via light. It is reported that Intel has now shipped over 8 million EICs (electro-optic integrated circuits).

In the foundry sector, Samsung has faced significant pressure in advanced processes in recent years, especially with pain points in yield and fluctuations with major clients. For Samsung, developing specialized processes (especially silicon photonics) is a more realistic "breakthrough card": once silicon photonics + CPO becomes the standard answer for the next generation of interconnects, it could become a key bargaining chip for reclaiming major clients, much like HBM did in the past.

This also explains why Samsung is accelerating resource gathering in silicon photonics: According to recent reports from South Korean media, Samsung Electronics has chosen silicon photonics as a core technology for the future, fully investing in talent and technology, intending to challenge TSMC in the "AI chip foundry" landscape. Samsung is mobilizing its global R&D network and has promoted senior executive Lee Kang-ho, who is responsible for silicon photonics, to vice president, and has hired former Intel Chief Product Officer researcher Park Hyun-dae.

Samsung has established a dedicated R&D center for silicon photonics in Singapore, a stronghold for silicon photonics technology. It is reported that Samsung is expanding its R&D scale in Singapore and poaching engineers from TSMC. The Singapore R&D center is led by vice president and former TSMC employee Choi Kyung-kyun, and is collaborating with companies like Broadcom to promote technology commercialization.

Industry insiders expect that CPO technology is likely to become Samsung's "counterattack trump card" against TSMC's leading position in the 2.5D and 3D advanced packaging market. Samsung has announced that the commercialization date for CPO is set for 2027, and real competition with TSMC is expected to begin then.

Samsung's approach is very similar to the narrative of HBM in the past: a technological point that, once it can leverage system architecture, may become a key bargaining chip in the next round of foundry competition. Given the market potential of silicon photonics technology, Samsung has positioned it as the "HBM of the foundry market."

GlobalFoundries (GF) Acquires AMF

GlobalFoundries announced on November 17, 2025, the acquisition of the silicon photonics foundry Advanced Micro Foundry (AMF) located in Singapore, aiming to accelerate its leading position in the silicon photonics field. This acquisition brings together AMF's manufacturing assets, intellectual property, and talent, making GF the largest pure silicon photonics foundry by revenue.

The logic behind GF's acquisition of AMF in Singapore is straightforward: silicon photonics is not just a technological route, but also about capacity and delivery cycles. Integrating AMF's manufacturing assets, IP, and talent is equivalent to locking in the "supply certainty" of silicon photonics in advance, while also emphasizing Singapore as a center of excellence for R&D and the route to expand to 300mm—this is a typical "platform expansion."

GF CEO Tim Breen stated, "The acquisition of AMF enables GF to provide a ten-year expansion and differentiation roadmap for pluggable transceivers and co-packaged optical devices, while accelerating the development of photonics in adjacent markets such as automotive and quantum computing." Tower Expansion

Due to the successful bet on silicon photonics as a distinctive process, the demand for wafer foundry services has surged, and Tower Semiconductor's stock price has doubled in just a few months, reaching a 20-year high.

As a result, Tower is accelerating its expansion. In the third quarter financial report of 2025, Tower announced an additional investment of approximately $300 million for its SiPho and SiGe businesses, aimed at capacity expansion and next-generation capability development, while also expanding its Fab 3 in Newport Beach and maintaining full load; the lease for the site has been extended by up to 3.5 years from the original expiration in 2027.

While investing in expansion, on November 12, Tower announced the launch of CPO foundry technology for the SiPho and SiGe platforms, emphasizing wafer bonding to stack PIC and EIC into 3D-ICs, and integrating the Cadence design process—this indicates that Tower aims to sell not just a single process, but an "importable delivery package."

Design Services: Giants Define Core CPO Capabilities

While foundries are responsible for making silicon photonics "work," design services and network chip giants determine whether CPO can be scaled. As the engineering level of CPO continues to rise, companies that possess optical interconnect IP, system-level integration capabilities, and complete interconnect platform solutions are becoming the "control point" players in the entire ecosystem.

Broadcom: Turning Silicon Photonics into a "Platform Business"

In the CPO arena, Broadcom is more like a player that "turns technology into a platform." It does not simply launch a standalone optical chip but provides a CPO platform solution that can be integrated, verified, and scaled around its own Ethernet switch ASIC and XPU system—this is why Broadcom often plays the role of "rhythm setter" in the silicon photonics supply chain: using roadmaps to pull the market from concept to engineering realization.

Broadcom's investment in CPO started early. In 2021, it completed concentrated exposure to the industry and capital markets; then in March 2022, it showcased the world's first 25.6T CPO demonstration at OFC, establishing the feasibility of high-bandwidth CPO; in October of the same year, it collaborated with Tencent and Ruijie to produce a 25.6T product-level demonstration, further advancing from "can run" to "can be used in a data center context." Entering 2023, Broadcom raised the bandwidth to 51.2T: demonstrating the product form in March, entering sampling in June to support early customer integration and testing, and showcasing a prototype demonstration in October, continuously compressing the cycle from validation to engineering maturity. By October 2024, its solution began to enter rack-level scenarios closer to real deployment—completing the TH5 Bailly demonstration in the OCP Rack; and in April 2025 at OFC, Broadcom further presented the "industry's first 6.4T XPU-CPO" milestone, indicating that CPO is moving from the switching side towards deeper integration with the computing side Entering a more scalable stage.

Key milestones achieved by Broadcom since launching its CPO initiative in 2021 (Source: Broadcom)

From the product perspective, Broadcom's CPO switch essentially represents an integrated solution that "directly embeds the optical engine into the switch chip I/O," addressing the core needs of high-radix and high-bandwidth networks, providing direct high-speed optical I/O for switch ASICs. Its integrated engine can deliver data rates of up to 6.4Tb/s and supports direct optical connections of approximately 2 km, covering typical data center network layers such as TOR (Top of Rack), leaf, and spine. The corresponding switch platforms have also formed a clear hierarchy: targeting the next generation of higher bandwidth at 102.4Tb/s (200G SerDes), mainstream evolution at 51.2Tb/s (100G SerDes), and earlier 25.6Tb/s level solutions.

More critically, Broadcom packages these capabilities with its advanced packaging and wafer-level integration processes, aiming for an engineering path of "scalable production" rather than remaining in laboratory demonstrations.

(Source: Broadcom)

Marvell's Major Acquisition of Celestial AI

Marvell's layout in the data center interconnect field is upgrading at an unprecedented speed. On December 2, Marvell announced it would acquire Celestial AI for at least $3.25 billion (cash + stock), with the total price potentially increasing to $5.5 billion if the latter meets revenue milestones. For Marvell, this is not just a "single-point technology enhancement," but an attempt to incorporate optical interconnect capabilities into its network and interconnect landscape, further providing a more complete connection platform and component combination to customers investing heavily in AI infrastructure.

Celestial AI's core asset is its optical interconnect hardware architecture for high-performance computing (referred to as "photonic fabric"), aimed at connecting a large number of chips into a whole with higher throughput and lower energy consumption. The company was reportedly valued at $2.5 billion during its financing in March this year and attracted Intel CEO Lip-Bu Tan to join its board in January—indicating that "optical interconnect" is upgrading from peripheral components to a strategic resource at the system architecture level More notably, Marvell has provided a roadmap: the first application of Celestial technology will target system interconnects composed of "large XPUs," with plans to gradually integrate these optical capabilities into custom AI chips and related devices such as switching chips. On the financial side, Marvell disclosed a third-quarter earnings per share of $0.76 and revenue of $2.08 billion, while providing guidance for fourth-quarter revenue of $2.2 billion, which also supports its narrative of "increasing investment in data center interconnects."

Entry of XPU Chip Manufacturers

If foundries and network chip companies are building the "infrastructure" for CPO, then the ultimate deciders of the commercialization pace of CPO are undoubtedly the XPU manufacturers. This is because only the network bandwidth demands of GPUs/AI accelerators can drive the true realization of silicon photonics and co-packaged optics.

In this migration, NVIDIA is the "accelerator" on the demand side, AMD is the filler, while Intel is the deepest foundational contributor to the silicon photonics ecosystem.

NVIDIA: The largest demand side for CPO, also the system definers

In terms of silicon photonics, NVIDIA's approach is very "engineering-oriented": rather than first discussing how impressive the devices are, it focuses on building the network to handle "million GPU-level" traffic. When 800G/1.6T interconnects push copper wires to their limits, NVIDIA's chosen answer is to place the optical engine directly next to the switching chip—this is its bet on CPO (co-packaged optics).

NVIDIA has repeatedly revealed that CPO will be integrated into its Rubin series by 2026, with an expected output value of up to $10 billion. In October of this year, NVIDIA also announced significant progress in the field of silicon photonics. The first co-packaged optical device (CPO) switch, Spectrum-X—currently adopted by major manufacturers such as Oracle and Meta—improves energy efficiency by 3.5 times compared to traditional networks, enhances network resilience by 10 times, and increases deployment speed by 1.3 times.

NVIDIA's actions indicate one thing: CPO is no longer just an upgrade in optical communication technology, but a necessity for GPU networks in the era of large models. Only system players of NVIDIA's scale can truly push CPO from the laboratory to industrialization at a scale of thousands of units.

AMD Acquires Optical Interconnect Startup

While NVIDIA is promoting the scaling of CPO and Intel is solidifying the foundational ecosystem of silicon photonics, AMD is accelerating its positioning through acquisitions, research and development layouts, and thermal roadmap.

In May of this year, AMD acquired the U.S. startup Enosemi—a company focused on AI interconnects, integrated photonics, and CPO development. This is not a financial investment, but rather AMD's "capability acquisition" in response to future AI system interconnect demands. Enosemi had previously collaborated with AMD on photonic technology, and its photonic chips are manufactured by GlobalFoundries, which is the manufacturing business AMD spun off years ago, providing AMD with a natural space for supply chain and process synergy Next is the "landing site." According to reports from Taiwanese media and industry organizations, AMD plans to establish R&D centers in Tainan and Kaohsiung, focusing on silicon photonics, AI, and heterogeneous integration, and will receive subsidies through Taiwan's Economic Department's "A+ Global R&D Innovation Partnership Program": the total investment is approximately NT$8.64 billion, with government subsidies of about NT$3.31 billion and AMD's self-funding of about NT$5.33 billion. The report also mentioned that AMD will collaborate with local industries and universities to promote the formation of a silicon photonics ecosystem and industrial cluster.

Intel: The Pioneer of the Silicon Photonics Ecosystem

In contrast to NVIDIA's high-profile advancements and Broadcom's roadmap-style iterations, Intel appears unusually low-key in the CPO field. However, from an industrial perspective, Intel is currently the deepest "infrastructure player" in the silicon photonics ecosystem.

As early as 2016, before the AI wave had taken off, Intel was the first to apply silicon photonics technology to commercial transceivers and build a complete electro-optical integrated circuit (EIC) manufacturing system. In recent years, Intel has shipped over 8 million EIC devices—making it the earliest and largest among all manufacturers.

Intel's leadership does not stop at the device level. In recent years, as AI has imposed extreme bandwidth demands on interconnects, Intel's early layout has begun to pay off: it has the world's most mature silicon photonics mass production supply chain, a complete optical co-packaging process route (which first demonstrated the CPO proof of concept), and has accumulated deep experience in data center communications (for example, collaborations on optical interconnects with AWS and Google), long-term partnerships with manufacturers like GlobalFoundries, Tower, and Ayar Labs, and has long served as a core contributor to OIF optical interconnect standards, leading the formulation of some industry silicon photonics interconnect standards.

With the arrival of the next round of data center architecture windows from 2026 to 2030, we also hope to see Intel's long-term layout enter a realization cycle.

Conclusion

This "optical chip" harvesting battle is not only a competition of silicon wafer capacity and advanced packaging technology but also a strategic showdown for chip giants to reshape the data center interconnect architecture in the AI era. With the full commercialization of CPO technology expected by 2027, the 3D integration technology of foundries, the IP integration of design service providers, and the system-level solutions of chip giants will jointly determine the upper limit of the next generation of AI computing power.

On the eve of the CPO explosion, domestic silicon photonics must also accelerate its start, shorten the gap, and achieve breakthroughs at this industrial juncture.

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