<div id="readability-page-1"><div>//php echo do_shortcode('[responsivevoice_button voice=&#34;US English Male&#34; buttontext=&#34;Listen to Post&#34;]') ?&gt; High-bandwidth memory, a critical component in modern AI systems—particularly for running large-scale training models—was a centerpiece at CES 2026, with the memory trio of Micron, Samsung, and SK hynix holding their HBM4 cards. It was all about telegraphing the readiness of HBM4 devices, which address the “memory wall” that threatens to plateau AI scaling.HBM4 is promising a solution to the memory wall—the bottleneck where data processing speeds outpace the ability of memory to feed that data to the processor—by carrying out the most significant architectural overhaul of high-bandwidth memory technology. It is purpose-built for next-generation AI accelerators and data center workloads to deliver major gains in bandwidth, efficiency, and system-level customization.HBM4, the sixth-generation high-bandwidth memory technology, does that by moving beyond incremental speed bumps to a complete redesign of the memory interface; it nearly triples the performance of early HBM3 devices that powered the first wave of the generative AI boom. <figure><img height="371" src="https://imageproxy.pbkrs.com/https://www.eetimes.com/wp-content/uploads/image_fa6d0f.jpeg/query-cmVzaXplPTYxNiwzNzE?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" width="616" original-src="https://imageproxy.pbkrs.com/https://www.eetimes.com/wp-content/uploads/image_fa6d0f.jpeg/query-cmVzaXplPTYxNiwzNzE"/></figure>HBM4, a generational leap in semiconductor technology, is rewriting the rules of AI infrastructure. (Source: SK hynix) HBM4 represents another fundamental shift in memory architecture by integrating logic die and turning the memory stack into a co-processor that can handle basic data before it reaches the main AI processor. That marks the end of the compute-only era while transforming memory from a passive storage bin to an active component. The primary driver of the HBM4 frenzy is Nvidia’s Rubin GPU platform, now in production and positioning itself as the initial and exclusive consumer of early HBM4 devices. Micron, Samsung, and SK hynix have reportedly started delivering HBM4 samples to Nvidia, and they are planning to begin mass manufacturing of HBM4 chips in 2026.<h3>SK Hynix at CES 2026</h3>At CES 2026, SK hynix, the current HBM leader commanding more than 50% of the global market, unveiled a 16-layer HBM4 device with 48 gigabytes of capacity. By stacking DRAM up to 16 layers, it significantly boosts both capacity and speed, achieving bandwidth exceeding 2 TB per second. SK Hynix is planning to begin mass production of these HBM4 devices in the third quarter of 2026.<figure><img height="567" src="https://imageproxy.pbkrs.com/https://www.eetimes.com/wp-content/uploads/image_681059.jpeg/query-cmVzaXplPTY0MCw1Njc?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" width="640" original-src="https://imageproxy.pbkrs.com/https://www.eetimes.com/wp-content/uploads/image_681059.jpeg/query-cmVzaXplPTY0MCw1Njc"/></figure>The transition to 16-layer HBM4 stacks presents formidable engineering challenges. (Source: SK Hynix)SK Hynix utilized its proprietary Mass Reflow Molded Underfill (MR-MUF) technology to thin individual DRAM wafers to a staggering 30 µm to fit within JEDEC’s strict 775-µm height limit. Here, MR-MUF heats and interconnects all the vertically stacked chips in HBM products, making it more efficient.Another notable highlight of SK Hynix’s 16-layer HBM4 device is the Korean memory giant’s alliance with TSMC to incorporate 12-nm logic as the base die, serving as the control logic or brain of the HBM4 stack. This shift from memory-based nodes to logic nodes effectively turns HBM4 into a custom memory solution that can be tailored for specific AI workloads.<h3>Samsung is back</h3>Unlike SK Hynix, which has joined hands with TSMC for HBM4’s logic die, Samsung has manufactured the logic die in its foundry’s 4-nm process node while handling 3D packaging under one roof. That makes it the only HBM4 supplier with a turnkey solution that controls the entire stack from silicon to final packaging.Moreover, unlike SK Hynix, which employs traditional MR-MUF technology to manufacture 16-layer HBM4, Samsung is racing ahead with hybrid bonding, a process in which copper pads are fused directly to copper without the use of traditional micro-bumps. It significantly reduces stack height and improves thermal dissipation, and the industry sees it as a long-term solution to next-generation manufacturing challenges.However, Samsung’s most notable leap in the HBM4 realm comes with the adoption of 1c DRAM process technology, which significantly improves energy efficiency, according to Samsung sources. That is a critical advantage because data center operators have been struggling with the thermal demands of GPUs exceeding 1,000 watts. According to TrendForce, Samsung has started production of its 1c DRAM with yields reportedly nearing its 80% mass-production target.<figure><img height="353" src="https://imageproxy.pbkrs.com/https://www.eetimes.com/wp-content/uploads/image_87cbdb.jpeg/query-cmVzaXplPTY0MCwzNTM?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" width="640" original-src="https://imageproxy.pbkrs.com/https://www.eetimes.com/wp-content/uploads/image_87cbdb.jpeg/query-cmVzaXplPTY0MCwzNTM"/></figure>After falling behind SK Hynix in HBM technology, Samsung is attempting to differentiate its HBM4 offerings by enhancing its DRAM and logic die technologies. (Source: Samsung)While Samsung has delivered samples for Nvidia’s Rubin AI accelerators and is likely to qualify before SK Hynix and Micron, it has already passed Broadcom’s system-in-package (SiP) testing for Google’s latest-generation TPUs. So, after falling behind SK Hynix in past years, Samsung is bouncing back from its HBM3e setbacks.<h3>The HBM4 memory war</h3>Micron Technology, the third member of the HBM troika, has also met Nvidia’s HBM4 specifications for Rubin AI accelerators, and it has delivered final customer samples. The Boise, Idaho-based memory chipmaker has been aggressively expanding manufacturing capacity for its 12-layer, 36 GB HBM devices featuring a 2,048-bit interface. It is targeting a capacity of 15,000 wafers dedicated to HBM4 manufacturing by the end of 2026.Meanwhile, industry reports claim that Nvidia revised the HBM4 specifications for its Rubin GPUs in the third quarter of 2025, raising the required per-pin speed to above 11 Gbps. As a result, Micron, Samsung, and SK Hynix resubmitted HBM4 samples and continue to refine their designs in response to Nvidia’s more stringent requirements.Nevertheless, HBM4 is poised to become a foundational technology that will determine AI accelerators’ ability to train next-generation agentic AI models. No wonder the HBM trio of Micron, Samsung, and SK Hynix is diverting massive amounts of wafer capacity away from traditional DDR5 and mobile memory.As we enter 2026, the memory industry is closely watching early production yields of HBM4 devices from Micron, Samsung, and SK Hynix—and 2026 is likely to be another landmark year for these memory chipmakers.<h5>See also:</h5>JEDEC finalizes HBM4 standardHBM Innovation Outpaces Standards DevelopmentSK hynix Maintains Memory Leadership with First HBM4 </div></div>

High-bandwidth memory (HBM4) was a key focus at CES 2026, with Micron, Samsung, and SK hynix showcasing advancements. HBM4 addresses the memory wall in AI systems, promising significant improvements in bandwidth and efficiency. SK hynix revealed a 16-layer HBM4 device with 48GB capacity, while Samsung introduced a unique 1c DRAM process for better energy efficiency. Micron is also ramping up production of its HBM4 chips. The competition among these companies highlights the ongoing evolution in memory technology for AI applications.

- High-bandwidth memory (HBM4) was a key focus at CES 2026, showcasing advancements from Micron, Samsung, and SK hynix.  
- HBM4 promises significant increases in bandwidth and efficiency, designed to tackle the "memory wall" that hampers AI performance, with industry leaders preparing for mass production in 2026.  
- The competition among these manufacturers reflects ongoing innovations in memory architecture, with enhanced capabilities to meet the demands of next-generation AI accelerators.

The State of HBM4 Chronicled at CES 2026