Performance Boosters to Scale Monolithic CFET Across Multiple Logic Technology Nodes

SHENG YANG, Researcher, ANNE VANDOOREN, Principal Member of Technical Staff, GEERT HELLINGS, Program Director XTCO/compute density, and NAOTO HORIGUCHI, Director CMOS Device Technology at imecComplementary FET (CFET) device architectures are expected to succeed gate-all-around (GAA) nanosheet transistors in the logic technology roadmap. In a CFET device, n and pMOS transistors are stacked on top of each other, removing the n-p separation from standard cell height considerations for the first time. As such, CFET device architectures have the potential to substantially shrink logic standard cell sizes, provided they can be combined with advanced technologies for contacting and powering the transistors.Of all possible integration flows, monolithic CFET (mCFET) is considered the least disruptive – offering the fastest path to CFET introduction at industry-relevant dimensions. With monolithic integration, the vertical device structure with common top and bottom gates is patterned and processed in a single sequence of process steps.The vertical stacking of layers brings along several challenges, and CFET-specific modules are needed to enable vertical isolation in critical parts of the stack cross-section. An example is the middle dielectric isolation (MDI) module, providing isolation between the top and bottom gates [1]. This allows different threshold voltages to be set for the top and bottom devices.In recent years, considerable progress has been made in demonstrating the critical building blocks for a 300mm mCFET integration flow. At VLSI 2024, imec researchers reported on a mCFET device with MDI module, compatible with an inner spacer – a nanosheet-specific feature that isolates the gate from the source/drain (S/D) [2]. At IEDM 2024, imec experimentally demonstrated a functional mCFET with direct backside contact to the S/D of the bottom pMOS device [3].Imec anticipates the introduction of the mCFET device architecture in the A7 node of the logic technology roadmap, when mCFET takes over from the outer wall forksheet (FIGURE 1). The latter is envisioned to extend the nanosheet-based logic roadmap into the A10 node, in anticipation of the mCFET being ready for mass production.Figure 1. Imec’s logic technology roadmap, showing the extension of the nanosheet era from 2nm to A10 node with the outer wall forksheet, before transitioning to CFET for A7 and beyond.Extendibility of mCFET to further nodes: an industry concernAt circuit level, imec proposed the double-row CFET architecture as the most optimal way to integrate mCFETs into an A7 standard cell [4]. A double-row CFET standard cell contains two rows of stacked devices with a shared vertical signal via in between, and ‘VSS’ power walls at the cell boundary. At IEDM 2024, imec showed through a design-technology co-optimization (DTCO) study how this double-row CFET architecture offers the best trade-off between manufacturability and area efficiency for the A7 technology node (FIGURE 2).Figure 2. Conceptual representation of (a) a single-row and (b) a double-row CFET.However, industry has always been reluctant to switch to a new device architecture as this entails huge tool investments and additional risks. For the transition to be successful, it is important that the new architecture can be used across different nodes.The imec researchers therefore continued their DTCO study to investigate the scalability of the double-row mCFET into subsequent technology nodes.Click here to read the full article in Semiconductor Digest magazine.