SK Hynix is developing an innovative packaging technology for next-generation high bandwidth memory, attempting to break through the performance bottleneck of HBM4 without significantly increasing capital expenditures.
According to TrendForce citing ZDNet on Tuesday, industry insiders revealed that SK Hynix is advancing a packaging architecture improvement plan, with core measures including increasing the thickness of DRAM chips and reducing the interlayer spacing of DRAM. This technology is currently in the validation stage. If successfully commercialized, this plan is expected to help SK Hynix achieve the top performance metrics set by NVIDIA for the sixth generation HBM4 and lay the foundation for performance improvements in subsequent products.
For the market, the potential significance of this technology lies in its low capital investment attribute—if mass production is realized, SK Hynix is expected to further consolidate its technological leadership in the HBM competitive landscape while providing more competitive memory solutions for downstream customers like NVIDIA. However, the report also pointed out that expanding this technology to large-scale mass production may still face challenges.
<h2>Increasing DRAM Thickness to Enhance Stability, Reducing Interlayer Spacing to Improve Efficiency and Transmission Rate</h2>
The core constraint on HBM4 performance improvement stems from its I/O count doubling to 2048 compared to the previous generation. Reports indicate that a denser I/O layout significantly enhances bandwidth but also greatly increases the risk of signal interference. Meanwhile, efficiently transmitting voltage from the bottom logic chip to the top DRAM also poses technical challenges in power supply.
These two challenges point to the need for optimization in packaging architecture, which is precisely the starting point for SK Hynix's technological exploration.
The first core measure of SK Hynix's new plan is to moderately increase the thickness of the upper DRAM chips. Traditional processes typically thin DRAM through back grinding to meet the overall height requirement of 775 microns for HBM4. However, excessive thinning can lead to performance degradation and make the chips more sensitive to external shocks.
By increasing DRAM thickness, SK Hynix aims to enhance the overall structural stability of HBM4, thereby reducing the risk of yield loss caused by physical stress.
The second measure is to reduce the interlayer spacing of DRAM. Without increasing the overall height of the package, tighter interlayer arrangements help accelerate data transmission speeds and reduce the power consumption required to deliver voltage to the top DRAM.
However, narrowing the interlayer spacing brings new process challenges: the injection stability of the MUF (molded underfill) will significantly decrease. As a protective and insulating material, uneven filling or voids in the MUF will directly lead to chip defects.
To address this, SK Hynix has developed a new packaging technology, with the core idea of achieving reduced DRAM interlayer spacing while maintaining stable yield without making large-scale changes to existing process flows or equipment. Recent internal tests have reportedly yielded positive results.
<h2>Promising Commercialization Prospects, Yet Mass Production Challenges Remain</h2>
If this technology is successfully commercialized, its most significant advantage lies in enhancing HBM performance without large-scale capital expenditures, which is of great importance for semiconductor manufacturers seeking a balance between cost-effectiveness in a highly competitive R&amp;D environment
However, the report also indicates that transitioning from the validation phase to large-scale production still poses challenges in terms of technological stability and process consistency. Currently, SK Hynix is actively advancing related verification work, and the commercialization timeline has not yet been clarified

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Core measures include increasing the thickness of DRAM chips and reducing the interlayer spacing of DRAM. Currently, this technology is in the verification stage. If successful in commercialization, this solution is expected to help SK Hynix achieve the top performance indicators set by NVIDIA for the sixth generation HBM4 and lay the foundation for performance improvements in subsequent products

- SK Hynix is developing an innovative packaging technology for next-generation high bandwidth memory to overcome HBM4 performance bottlenecks without significantly increasing capital expenditure.  
- The technology involves increasing DRAM chip thickness and reducing inter-layer spacing, currently in the validation phase, which could help meet NVIDIA's performance targets for HBM4.  
- If successful, this approach may enhance SK Hynix's competitive edge while providing more competitive memory solutions, but challenges remain in achieving stable mass production.

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Report: SK Hynix is exploring new packaging technology for HBM4, aiming for NVIDIA's top performance targets