Supply-side constraints for artificial intelligence computing power infrastructure are spreading from front-end chip manufacturing to optical components and advanced packaging materials. A Broadcom executive has, for the first time, identified three major bottlenecks in the AI supply chain, revealing that the true choke points in this computing power arms race are far deeper than widely recognized by the market and difficult to resolve in the short term.
Natarajan Ramachandran, Director of Product Marketing for Broadcom's physical layer products, stated at a media briefing in Taipei on March 24 that the AI-related supply chain currently faces three core bottlenecks: laser capacity, wafer (specifically TSMC's advanced processes), and PCBs (Paddle Cards, printed circuit boards). The lead time for small PCBs used inside high-speed optical transceivers has surged from about six weeks to approximately six months, and this is not expected to ease until 2027.
The direct implication of the above statement for the market is that the investment boom in AI infrastructure cannot automatically resolve supply-side structural constraints. From laser yields below 30% under stringent testing, to low initial output from TSMC's advanced packaging, to PCB suppliers requiring over six months for changeover certification – multiple bottlenecks are stacking up, meaning the computing power capacity gap is likely to persist structurally, and supply chain price increases may become normalized.
Broadcom CEO Hock Tan also confirmed at the March earnings call that Broadcom has secured supplies of critical components, including advanced process wafers, high-bandwidth memory (HBM), and substrates, for 2026 to 2028. This proactive procurement itself is a direct reflection of the current supply tightness.
<h2>PCB Lead Times Surge Tenfold</h2>
In 800G/1.6T high-end optical transceiver modules, PCBs are critical interfaces connecting external cables to internal optoelectronic components. These small PCBs, due to their extremely small space and the need to handle very high-frequency signals, typically use the mSAP (modified semi-additive process) manufacturing method. The technical threshold is far higher than that of ordinary PCBs, and they are mainly supplied by manufacturers with advanced HDI or IC substrate technology.
The root cause of PCBs becoming a bottleneck lies in process overlap. Their mSAP process has some overlap with the IC substrate process required for AI servers. When the world is scrambling for HBM capacity, the capacity for small PCBs is squeezed accordingly. At the same time, 1.6T modules have extremely stringent requirements for signal quality, demanding PCBs made with ultra-low loss materials and precise impedance control, which not all PCB manufacturers can handle.
More critically, the certification period for switching suppliers is more than six months. This is precisely why hyperscale cloud vendors like Google and Meta are willing to sign three- to four-year long-term contracts to secure the capacity of existing suppliers.
<h2>Lasers: Yields Below 30%, Indium Phosphide Capacity is the Core Bottleneck</h2>
Laser components have become another major bottleneck in the era of CPO (Co-packaged Optics). To support 1.6T and even higher bandwidth, lasers must maintain wavelength stability in the high-temperature environment of data centers, requiring stringent &#34;ultra-high power&#34; and &#34;ultra-low noise&#34; continuous-wave (CW) lasers. Even if suppliers can produce laser dies, the yield that meets the high standards of CPO after rigorous reliability testing may be less than 30%.
Capacity constraints are also severe. High-power lasers rely on Indium Phosphide (InP) technology, and there are only a handful of manufacturers globally capable of large-scale 6-inch InP mass production. If upstream InP epitaxial wafer manufacturers or companies with their own capacity like Coherent and Lumentum are overwhelmed with orders, downstream packaging plants will have no laser dies to use, regardless of their quantity.
A deeper structural pressure comes from the amplification effect of CPO architecture on laser demand. In traditional optical modules, one module is configured with one laser; in the CPO solution, to reduce thermal impact, the industry is shifting to an ELSFP (External Laser Small Form Factor Pluggable) architecture. This causes the demand for laser dies to no longer be linear with the number of switches, but to increase exponentially, directly impacting the already tight InP epitaxial capacity.
<h2>Wafers and Advanced Packaging: The Real &#34;Super Traffic Jam&#34; is in Back-end Processes</h2>
Regarding wafer supply, Natarajan Ramachandran directly stated that &#34;TSMC's capacity is at its limit,&#34; predicting that TSMC's advanced process lines will face bottlenecks in 2026, despite TSMC's plans for continuous expansion until 2027.
However, the real &#34;super traffic jam&#34; occurs in the back-end advanced packaging stage. Entering the CPO era, TSMC needs to adopt COUPE (Compact Universal Photonic Engine) technology, using hybrid bonding to vertically stack optical chips and silicon chips. This new packaging technology is extremely difficult, and the testing cycle is very long, making it hard to quickly increase initial unit output per hour (UPH).
The competitive landscape further intensifies capacity pressure. In 2026, Broadcom's competitors for capacity will not only be traditional network communication manufacturers but also NVIDIA, Apple, AMD, Qualcomm, and Google, Meta, and OpenAI, which are heavily investing in developing their own ASICs. When the most cutting-edge AI computing chips and the highest-end 1.6T network switches enter the same TSMC production line, capacity is essentially entering a &#34;rationing system.&#34;
Even if TSMC decides to massively expand production now, the delivery time for factory construction, cleanroom completion, the introduction of ASML's extreme ultraviolet (EUV) lithography equipment, and various high-end testing equipment is typically twelve to eighteen months. This means that the capacity for 2026 has effectively been locked in by major manufacturers between 2024 and 2025 – customers placing new orders now will have to wait until 2027 for new capacity to be released.
<h2>Chain-wide Spillover: Lagging Expansion by Second-tier Suppliers, Bottlenecks Spread</h2>
Capacity pressure is spilling over to the entire supply chain. Advanced packaging is not just the responsibility of packaging plants; the truly bottleneck-prone areas include: the ABF substrates required for CoWoS, the underfill required for advanced packaging, the heat dissipation demands brought by explosive AI power consumption, KGD testing and burn-in testing, CPO and optical modules, and the dicing and drilling of TSV and interposers.
TSMC Chairman C.C. Wei once stated that &#34;CoWoS capacity is still insufficient&#34; – he lacks not capital, but the capacity of supporting suppliers: substrate manufacturers, probe card manufacturers, underfill suppliers, etc. TSMC can invest heavily in building factories but cannot force these small and medium-sized suppliers to double their capacity in a short period. ABF substrate expansion takes two to three years, aging tests are extremely long, and the alignment tolerance for optical array positioning is in the sub-micrometer range, making full automation difficult – each step slows down the overall pace.
As NVIDIA continues to push hardware iterations in GPU architecture, supply chain bottlenecks and price increases may become a structural norm rather than a cyclical disturbance. For investors, the location of capacity bottlenecks is where pricing power is concentrated.

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Broadcom executives highlighted three core bottlenecks in the AI supply chain: lasers, advanced process wafers, and PCBs. Limited by technical barriers and capacity constraints, lead times for small PCBs have surged to six months, with laser yields below 30%. Even with TSMC's massive capacity expansion, equipment lead times are 12-18 months, and capacity for 2026 is largely locked in by major players, pushing new orders to 2027. The computing power shortage is expected to become normalized

- The supply chain for AI infrastructure is facing significant constraints, extending from chip manufacturing to optical components and advanced packaging materials.  
- Key bottlenecks include limited laser production capacity, slow delivery times for high-frequency PCBs, and impending restrictions in TSMC's advanced wafer production anticipated by 2026.  
- These ongoing supply challenges suggest that increased investment in AI infrastructure may not alleviate structural supply-side constraints, potentially leading to persistent price increases across the industry.

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AI Computing Power's Fatal Flaw! Broadcom Director Points to "Three Major Bottlenecks," Capacity Gap Likely to Persist Until 2027