Intel's next-generation CPU &#34;Meteor Lake&#34; is set to be released this month (September). Meteor Lake adopts Intel's most advanced second-generation 3D IC packaging technology, &#34;Foveros,&#34; which enhances chip performance through stacked packaging.
As Moore's Law gradually loses its effectiveness due to the physical limits of process iteration, improving packaging technology has become a new technological endeavor to continue Moore's Law, even with the use of SiC materials.
Pat Stover, Senior Director of Packaging/Assembly and Test Technology Development at Intel, said, &#34;I have 27 years of experience in the packaging field, and packaging technology has extended Moore's Law.&#34;
The improvement of packaging technology is referred to as &#34;advanced packaging.&#34;
In simple terms, advanced packaging is like stacking and combining chips like LEGO blocks, and then sealing and solidifying these combinations into a whole. This is a three-dimensional solution to the miniaturization barriers caused by physical limitations. TSMC, Intel, Samsung Electronics, and others are all increasing their research and development investment in this technology.
Intel has made significant packaging investments in the Asia-Pacific region, with Malaysia being the chosen country. It seems that Intel wants to carve out a piece of the packaging landscape dominated by TSMC, but based on the current progress, it has not yet reached the moment when it can truly threaten TSMC.
What are the similarities and differences between 2.5D/3D packaging?
In general, advanced packaging refers to packaging technologies above 2.5D. 2.5D refers to stacking partial chips, while 3D achieves full stacking.
Currently, Apple's M1 Ultra chip uses TSMC's InFO packaging technology (InFO_Li), which is 2.5D. NVIDIA's AI chip uses TSMC's CoWoS packaging stacking technology, also known as &#34;3D IC.&#34; However, some technical papers claim that TSMC's CoWoS is also a 2.5D packaging technology. TSMC's SoIC technology belongs to 3D packaging.
2.5D/3D IC packaging are both emerging semiconductor packaging technologies that achieve high-speed and high-density interconnection between chips, thereby improving system performance and integration.
The difference between the two lies primarily in the connection method. 2.5D packaging connects chips through TSV silicon interposer substrates, placing two or more active semiconductor chips side by side in the silicon interlayer to achieve high-density interconnection of multiple/group chips. 3D IC packaging stacks multiple chips/groups vertically and achieves interconnection between chips through direct bonding technology. The characteristic is that the interconnection between chip groups is shorter and the size is smaller compared to 2.5D packaging.
Secondly, the manufacturing processes are different. 2.5D packaging requires the production of silicon-based interlayers and complex processes such as lithography. The manufacturing process of 3D IC packaging involves the application of direct bonding technology, which is highly challenging.
Thirdly, the application scenarios and performance differ. 2.5D packaging is widely used in high-performance computing, network communication, artificial intelligence, and mobile devices, with higher performance and relatively more flexible design.
3D IC packaging is commonly used in fields such as memory, sensors, and medical devices. It has high integration and relatively smaller package size.
Intel's 2.5D packaging technology, known as &#34;EMIB,&#34; has been applied in products since 2017. Unlike general 2.5D packaging technologies, EMIB does not require a TSV interposer. Therefore, no additional processes are needed, and the design is relatively simple. Intel's data center processor, Sapphire Rapid, utilizes this technology. Intel's first-generation 3D IC packaging, called &#34;Foveros,&#34; was used in their previous generation computer processor, Lakefield, in 2019.
In terms of technical features, EMIB connects various chips (die), including high-bandwidth memory (HBM) and computing units, from below through a &#34;silicon bridge&#34; instead of a TSV interposer. Since the silicon bridge is embedded in the substrate and connects the chips, it achieves a direct connection between high-bandwidth memory and computing chips, thereby improving the chip's energy efficiency.
Foveros adopts 3D stacking, where chips with different functions, such as high-bandwidth memory, computing units, and architectures, are stacked like a hamburger and interconnected by copper wires penetrating each layer of the chip stack, similar to inserting chopsticks into a hamburger. Finally, the completed stacked chips are sent to the packaging factory for assembly, where the copper wires are bonded to the circuits on the circuit board.
Intel's upcoming next-generation CPU, &#34;Meteor Lake,&#34; which will be released in September, will adopt the second-generation &#34;Foveros&#34; 3D IC technology.
Currently, TSMC's CoWoS packaging technology has insufficient capacity. There are reports that Apple has reserved most of TSMC's CoWoS packaging capacity, forcing Qualcomm to transfer some chip orders to Samsung Electronics. Currently, Samsung Electronics' 3D packaging technology is known as &#34;X-Cube.&#34;
In terms of the breadth and depth of application of these two packaging technologies, 3D packaging technology is still in its early stages, and 2.5D packaging technology has not been fully scaled.
One interesting point, as revealed by Pat Stover, is that under Intel's IDM2.0 strategic guidance, even if customers do not place orders at the wafer foundry, they can still use advanced packaging services. This indicates that Intel is shifting from a &#34;product-oriented&#34; approach to a &#34;customer-oriented&#34; approach, no longer emphasizing a product-centric mindset, but instead transitioning towards a &#34;customer demand customization&#34; business model.
For example, customers can directly complete the packaging at Intel without being obligated to go through all the chip manufacturing processes at Intel's foundry.
<h2>Where are the overseas packaging and testing core centers located?</h2>
Intel's upcoming new generation CPU, &#34;Meteor Lake,&#34; which will be released in September, will adopt their own 3D IC packaging technology, &#34;Foveros,&#34; and the packaging process will also be completed in their own factories.
Intel's advanced packaging efforts are serious.
In late August, there were reports that Steven Long, Vice President and General Manager of Intel Asia Pacific, stated that Intel is currently building its latest packaging facility in Penang, Malaysia to strengthen its 2.5D/3D packaging layout. This will be the first 3D packaging facility outside the United States to adopt Intel's advanced Foveros packaging architecture, following the ones in New Mexico and Oregon.
According to Intel's plans, by 2025, Intel's Foveros packaging capacity will reach four times the current level. The new Penang facility will become Intel's largest 3D packaging facility. In addition, Intel will also build another packaging and testing facility in the Kulim Hi-Tech Park in Malaysia. In the future, Intel's packaging and testing facilities in Malaysia will increase to six.
At the Intel On Technology Innovation Summit held at the end of 2022, Intel CEO Gelsinger stated that Intel's foundry services will usher in the &#34;system-level foundry era.&#34; Unlike the traditional foundry model of only supplying wafers to customers, Intel also provides multiple services such as silicon, packaging, software, and chiplets. In addition, from Pat Stover's description, it can be seen that Intel has &#34;disassembled/integrated&#34; various aspects of chip manufacturing, allowing customers to choose in a more flexible manner.
It is worth mentioning that Intel's Foveros plan includes the introduction of Foveros Direct, which enables direct copper-to-copper bonding. Through Hybrid Bonding (HBI) technology, the bump pitch can be reduced to below 10 micrometers, achieving more than a 10-fold increase in interconnect density between different chips. This blurs the boundary between wafer manufacturing and advanced packaging, but also significantly increases the requirements for advanced packaging facilities.
According to Steve Long, Vice President and General Manager of Intel Enterprise and Asia Pacific Japan (APJ), Intel has investments in multiple countries in the Asia Pacific region, but the main focus is on Japan and Malaysia, especially the latter with the highest investment amount.
According to public investment records of Intel reviewed by Wall Street News, in the Asia Pacific region, Intel has invested in assembly and testing facilities in China (Chengdu) and Vietnam. As for packaging facilities, Intel currently has three facilities under construction or planning: one in New Mexico, USA (under construction), one in Penang, Malaysia (under construction), and one in Kulim, Malaysia (planned).
Currently, Intel has not disclosed the capacity data for Foveros. Based on the current situation, TSMC and Samsung Electronics do not need to be overly concerned about Intel's advanced packaging capacity. This is because Intel announced two years ago an investment of $3.5 billion to expand its advanced packaging capacity in New Mexico, which is still not completed. As for the completion time of the new Penang facility in Malaysia, it is estimated to be by the end of 2024 or early 2025.
In the future, Intel will have six facilities in Malaysia. The existing four include two packaging and testing facilities in Penang and Kulim, as well as the System Integration and Manufacturing Services (SIMS) facility and the Custom Device Packaging (KMDSDP) facility in Kulim, which are responsible for production testing equipment.
Vice President Suresh Kumar of Intel's Chipset Engineering Division stated that having design capabilities is a key feature of the Malaysian base. The same project can alternate with the R&amp;D team in Oregon, USA, allowing for uninterrupted 24-hour development. &#34;The Malaysian design team has a history of 32 years and, coupled with a nearly complete production line, the design speed here will also be faster.&#34;

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Track Hyper | Focusing on TSMC: Intel's Big Bet on Advanced Packaging