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Broadcom and Taiwan’s Powertech will invest US$400 million on a joint venture plant in Singapore for high-end chip packaging substrates, media report, citing Powertech regulatory filings. Powertech developed Fan-Out Panel-Level-Packaging (FOPLP) for large-sized chips such as those used in AI data centers. It also counts AMD as a client for FOPLP. $Broadcom(AVGO.US) $AMD(AMD.US) #Powertech #Singapore
Source: Dan Nystedt
Rumor: TSMC’s 2027 CoWoS packaging capacity will hit at least 200,000 wafers per month (wpm) – a conservative estimate – as the key packaging for AI chips remains in severe shortage, media report, citing unnamed supply chain sources. Nearly all of TSMC’s plant construction projects are running 24-hour shifts to accelerate the build out, partly due to competition from Intel and others.
The potential bonanza for CoWoS equipment makers is turning into a nightmare, amid rumors TSMC has not decided on order allocation yet. Some fear TSMC is holding back to force price cuts, and others say it takes 7-9 months to deliver equipment, so further delays might cause them to miss deadlines. Tidbits:TSMC’s CoWoS capacity (all wpm)2024: 30,000+2025: 70,0002026: 130,000 up from 110,000 target2027: 200,000+Market Hopes 240,000 to 260,000 by end 2027Nvidia still uses over 50% of CoWoS capacityGoogle, Amazon, other AI chips by CSPs have become a major growth engine for CoWoS into 2027.Nvidia has reserved most of TSMC’s SoIC packaging capacity as it ramps to an estimated 50,000wpm in 2027, up from prior estimate 10,000 to 20,000.TSMC’s schedule for SoIC and CoPoS packaging are already done, giving equipment makers visibility through late 2020sAMD turned to ASE, SPIL, Amkor for 50% of orders because it couldn’t get enough CoWoS. It’s also partnered with Powertech.ASE, Amkor, Powertech are expanding the most aggressively (after TSMC), so more orders for equipment makers. $Taiwan Semiconductor(TSM.US) $NVIDIA(NVDA.US) $AMD(AMD.US) $Alphabet(GOOGL.US) $Amazon(AMZN.US) $Advanced Semiconductor Engineering(ASX.US) $Amkor Tech(AMKR.US) #Powertech #semiconductorsSource: Dan Nystedt
TSMC’s inability to meet CoWoS demand has sent overflow orders to packaging specialists ASE, Powertech, media report, adding ASE raised its 2026 capex to US$8.5 billion from $7 billion to meet demand for Leading Edge Advanced Packaging (LEAP) related to AI servers, high-speed networking and automotive, which is projected to bring in revenue of $3.5B, up from $3.2B previously. $Taiwan Semiconductor(TSM.US) $Advanced Semiconductor Engineering(ASX.US) #Powertech
Source: Dan Nystedt
AMD’s new “Venice” CPU is already in 2nm mass production by TSMC, media report, citing AMD CEO Lisa Su, and adding “Verano”, another 6th-gen EPYC CPU, will also be 2nm. Venice is the first high performance computing (HPC) chip made on TSMC’s most cutting-edge manufacturing process. AMD has also already qualified the first panel-based EFB interconnect with Powertech (PTI), Taiwan, as AMD turns to FOPLP (Fan-out Panel-level-Packaging) for more cost-effective higher volume packaging. AMD is also working with ASE and SPIL on 2.5D bridge interconnects. $AMD(AMD.US) $Taiwan Semiconductor(TSM.US) $Advanced Semiconductor Engineering(ASX.US) #Powertech #semiconductors
Source: Dan Nystedt
