AVGO: Lagging Nvidia, now under siege from smaller rivals?

$Broadcom(AVGO.US) has sold off in recent weeks, driven by concerns around 'META selling compute' and 'key downstream customers seeking alternative supply options'. The former is a market beta issue, while the latter raises company-specific alpha risks.

Initially, investor focus on AVGO centered on its potential to counter NVDA's ecosystem. Now AVGO faces similar challenges, as major customers explore alternatives: 1) supply-chain diversification at GOOGL, and 2) Anthropic shifting orders from full-rack delivery to XPU core chips.

I. GOOGL supply-chain diversification

The long-standing 'GOOGL + AVGO' partnership carved out share in an AI chip market otherwise dominated by NVDA, with AVGO now at roughly 10–20% share. Since early this year, GOOGL has announced progress on supplier diversification, and AVGO management confirmed post-earnings that GOOGL is engaging other vendors.

Even after 10+ years of collaboration and strong results in AI silicon, the tie-up may be less binding than it appears. Signs point to a looser coupling.

① A second supplier for TPU

For the next-gen TPU, GOOGL is expected to launch TPU8i (inference) and TPU8t (training). Crucially, GOOGL will bring in MediaTek (MTK) to supply TPU8i, while AVGO continues to supply TPU8t. This marks the first time GOOGL is adding a second vendor to the TPU supply base.

② Deeper collaboration with MRVL

MRVL’s prior work with GOOGL centered on Axion3 CPUs, not data-center AI compute. Subsequent reports suggest GOOGL is discussing co-developing two new AI chips with MRVL, including a Memory Processing Unit (MPU) and a TPU variant focused on inference. At Computex in Jun, additional chatter indicated MRVL will supply custom networking silicon to GOOGL.

In short, for next-gen TPU8i (inference), GOOGL is building a multi-vendor, ‘de-AVGO’ architecture.

1) Why does GOOGL want to 'go solo'?

From GOOGL’s perspective, introducing MTK lowers cost (JP Morgan channel work suggests MTK’s solution is 40–50% cheaper) and enhances design control. Under AVGO’s prior 'turnkey' model, AVGO marked up materials and foundry steps, notably advanced packaging (CoWoS) and HBM procurement, with industry chatter pointing to 15–20% pass-through markups.

GOOGL now seeks to shift toward a COT model (Customer-Owned Tooling), taking on template design and direct procurement of wafer capacity and memory rather than relying on a single ASIC vendor for the entire stack. This rebalances cost and control.

2) What changed in the engagement model?

ASIC programs can be split into front-end and back-end: the front-end covers architecture definition, RTL, and IP integration; the back-end spans wafer fab, CoWoS packaging, HBM sourcing, test, and yield management. Under the legacy AVGO model, AVGO supplied critical front-end IP and executed the entire back-end. Under COT (e.g., with MTK), GOOGL largely takes the front-end, while parts of the back-end (standardized physical design, conventional packaging management) are assigned to MTK.

a) AVGO’s top-tier SerDes IP in the front-end (400G/lane) will not be licensed for non-AVGO tape-outs per AVGO policy. So under COT, GOOGL would opt for MTK’s in-house 224G SerDes or a third-party, lower-performance SerDes, which represents roughly 25–30% of total chip cost.

b) In the back-end, previously handled end-to-end by AVGO, GOOGL will outsource back-end design and standard manufacturing management to MTK in the COT model, while retaining full control of architecture/IP/system design. Tape-out capacity negotiations with TSMC and HBM procurement would be handled directly by GOOGL to avoid intermediary markups.

c) MTK’s back-end responsibilities include:

- Standardized physical back-end: MTK’s TPU8i uses a single-die approach (one compute die + one I/O die + six HBM3e stacks), which is far simpler than AVGO’s dual-die approach (two compute dies + one I/O chiplet + eight 12‑high HBM3e stacks). This avoids complex multi-die interconnect and ultra-high-speed SerDes signal challenges.

- Conventional packaging management: leverage mature CoWoS‑S/Intel EMIB‑T, rather than AVGO’s high-difficulty customized CoWoS‑L/3D SoIC.

Net-net, under the new model GOOGL handles the front-end, MRVL can supply networking/connectivity silicon, and MTK assists with parts of the back-end. Roles are more modularized.

3) Can GOOGL live without AVGO?

We think a full decouple is unlikely. Incremental training silicon should still come from AVGO, and whether TPU8i can reach volume production will be a gating factor for GOOGL’s broader COT pivot across v9/v10 and beyond.

MTK is tackling the relatively easier single-die design, yet the program has seen multiple delays. By contrast, AVGO starts volume on GOOGL’s dual-die products from TPUv7 in 2025, underscoring a meaningful delivery capability gap.

AMZN’s Trainium 1/2 followed a COT path and offers a reference case. AMZN acquired Annapurna Labs in 2015 for approx. $350 mn and spent a decade internalizing most core front-end and back-end flows; regardless of how long GOOGL’s internalization may take, the key difference lies in the choice of scale-up interconnect architecture.

Trainium’s scale-up fabric is PCIe-based, which has a standardized PHY with multiple commercial IP vendors (Synopsys/Cadence/Alphawave, etc.). GOOGL’s ICI/OCS is a proprietary high-bandwidth fabric, where top-end SerDes lacks standardized commercial substitutes, and AVGO will not license its top-tier SerDes IP for non-AVGO tape-outs. That means unless GOOGL changes its scale-up approach, its SerDes need remains, and there is still a generational gap between MTK’s 224G and AVGO’s 400G/lane SerDes.

What does 224G imply in practice? If MTK delivers, it would narrow the gap vs. AVGO and NVDA. That said, next-gen roadmaps at NVDA and AVGO move beyond 400G.

GOOGL seeks a balance between cost-down and performance, with MTK’s 224G targeted primarily at inference. If COT ramps smoothly, GOOGL both saves cost and gains bargaining leverage vs. AVGO.

Even if MTK lags AVGO technically, the price gap is large. Some checks suggest GOOGL’s v9 might deliberately step down from AVGO’s 400G SerDes to MTK’s 300G, implying v8i COT success if MTK leads v9; other work indicates the v8 COT team is still struggling with optimization. Given conflicting chatter, watch the long-term AVGO–GOOGL agreement, under which AVGO will develop and supply custom TPUs across multiple future gens.

We think the LT agreement raises supplier-lock certainty (albeit non-exclusive). Based on Trainium‑3 timelines, the concept‑to‑volume cycle is ~3 years, and partner selection typically finalizes ~18 months pre‑launch, making late-stage course changes difficult.

Taking advanced-node access, SerDes IP, front-end depth, leading chip/packaging design, and compute/network/memory architecture know‑how together, AVGO retains a lead today. With a 10‑year relationship in place, a full GOOGL–AVGO decouple looks unlikely in the near to mid term.

II. Anthropic’s order shift

AVGO’s Anthropic orders have shifted from full-rack delivery to XPU and other chips only. This directly lowers revenue expectations and stokes concerns about AVGO’s role in networking and connectivity.

First, 'full-rack delivery' does not mean AVGO manufactures cables or performs assembly. It is effectively a prime contract: physical manufacturing, assembly, and cable integration are executed by ODMs/OEMs/3rd parties, while AVGO provides chips, design, and system architecture, recognizing the entire rack as its revenue.

A rack includes ASIC/GPU, memory, networking components, power system, thermal/cooling, mechanicals, and system assembly. AVGO primarily supplies XPU, Ethernet switch silicon (Tomahawk), NICs, PCIe switches, SerDes/optical DSPs, plus scale‑up/scale‑out network solutions and reference designs for the full rack.

Using NVDA’s rack BOM as a proxy and the post‑adjustment revenue mix for Anthropic (100% → ~25%), we infer AVGO’s TPU/XPU share of its rack solution value (~25%) is well below NVDA’s. This underscores lower compute content weight in AVGO racks.

Source: MS, Dolphin Research

From Anthropic’s standpoint, the drivers are: 1) full-rack is convenient at small scale but uneconomic at larger scale; and 2) a desire to avoid dependence on GOOGL/AVGO and gain control of the value chain. Decomposing the GOOGL–AVGO TPU engagement shows GOOGL leads the three-tier network architecture and protocols across scale‑up/scale‑out/scale‑across, while AVGO contributes primarily at the PHY level with ASICs and SerDes.

1) Scale‑up (within a Pod): GOOGL‑led

① ICI: GOOGL’s in‑house chip‑to‑chip interconnect. Each Ironwood host has 4 TPUs; 64 TPUs per rack form a 'cube' connected via high‑speed ICI links in a 3D torus, enabling dense all‑to‑all topology. This is the fabric spine within a pod.

② OCS: optical circuit switching to stitch cubes into pods and superpods. Beyond a single cube, multiple cubes connect via a dynamically reconfigurable OCS optical network, scaling from 256‑chip pods up to 9,216‑chip superpods, with OCS underpinning fault tolerance.

At this layer, ICI and OCS are GOOGL‑owned. AVGO does not provide the 'connectivity solution' here; it supplies SerDes IP (e.g., 112G/224G), HBM controllers, and integrates them with GOOGL’s TPU compute core into an ASIC.

2) Scale‑out (intra‑DC, across pods): GOOGL defines, AVGO supplies core silicon

This tier runs on Ethernet DCN. GOOGL designs the network (Jupiter, and next‑gen Virgo), while AVGO supplies the core chips — Ethernet switch silicon (Tomahawk/Jericho) and Thor NICs. On AVGO silicon, GOOGL builds custom switch chassis and uses SDN to orchestrate traffic across the DC.

3) Scale‑across (inter‑DC): GOOGL network + software

The core technologies are coherent optical modules and core routers. AVGO contributes router silicon (Jericho) and coherent optical DSPs. GOOGL continues to use Jupiter as the front‑end network for inter‑DC traffic and leverages JAX/TensorFlow to shard training workloads, mitigating ms‑level latency across DCs.

Overall, in the AVGO–GOOGL partnership, GOOGL is the system architect (owning scale‑up OCS and integration), while AVGO supplies the critical chips at each layer: SerDes for scale‑up, Tomahawk for scale‑out, and DSPs for scale‑across. It is a clear division of roles.

Anthropic’s move from 'full rack' to 'XPU chips' is fundamentally about avoiding lock‑in to GOOGL/AVGO. Anthropic can still buy AVGO’s core chips, but choose GOOGL’s OCS switches, deploy in AMZN facilities, or build its own HW/SW stack for scale‑up and scale‑out. It keeps control rather than sit entirely under GOOGL’s architecture.

AVGO is primarily a chip seller. Under full‑rack delivery, it sells more chips (including pass‑through components), but with the shift to XPU only, AVGO secures roughly the XPU value (~25% of total), while Anthropic can source networking silicon from others (e.g., MRVL), introducing revenue uncertainty for AVGO’s connectivity stack.

Post‑shift, the XPU revenue is estimated at ~25% of the prior full‑rack revenue. At 1 GW of compute, full‑rack delivery implies roughly $20 bn of revenue, whereas shipping only chips (compute + networking) maps to about $5–10 bn.

Post‑earnings, AVGO management guided to >1 GW of AVGO TPU compute for 2026 and, in Apr, signed for an incremental 5 GW of next‑gen TPU compute starting 2027 (up from 3 GW). This implies Anthropic could contribute roughly $6–8 bn/$30 bn of revenue to AVGO in 2026/2027, down by about $13 bn/$30 bn vs. prior full‑rack assumptions.

III. Overall take on AVGO

Before the latest print, both GOOGL’s diversification and Anthropic’s order changes were already underway. Management’s confirmation that customers are exploring alternatives further amplifies concerns about AVGO’s competitive trajectory.

Customers seeking a 'plan B' is not about AVGO underperforming — GOOGL’s TPU8t remains fully with AVGO. It is primarily about unit economics in inference, where lower‑cost options are preferred. AVGO Semi’s GPM exceeds 65%, while MRVL and MTK run near 50%, and hyperscalers prefer to avoid markups on HBM and CoWoS.

Given MTK’s repeated delays on single‑die while AVGO ramps dual‑die for 2025, AVGO’s ASIC capability clearly leads MTK. MTK serves as GOOGL’s COT 'trial stone' and, if successful, becomes leverage to pressure AVGO pricing.

Anthropic’s shift from full‑rack to XPU reduces AVGO revenue per GW for Anthropic. AVGO will no longer benefit from pass‑through margins and must compete for networking/content wins. We still expect AVGO–Anthropic XPU collaboration to continue in 2026/2027 primarily on TPU, with potential co‑developed XPU in 2028; AVGO’s dual‑die remains a clear lead in ASIC, and GOOGL continues to rely on AVGO for TPU8t in training.

Because the Anthropic change predated earnings, most sell‑side models had already trimmed AI revenue. The market still expects FY2027 AI revenue ≥ $130 bn (vs. company’s conservative $100 bn guide). At a $1.7 tn mkt cap, AVGO trades at roughly 17x FY2027 core net profit (assumes ~76% revenue CAGR, Adj. GPM 69.4%, tax rate 9.5%).

With key customers diversifying, AVGO’s multiple has compressed toward NVDA’s (~15x PE). Both firms are strong in AI chips, but the market worries about the hunt for better TCO in inference leading to lost orders or share erosion. That overhang persists.

Hence NVDA’s emphasis on Gov./enterprise and sovereign cloud demand. AVGO, however, continues to frame concentration around 'six customers' this quarter, keeping investors uneasy about future competition and growth. If diversification at core accounts is inevitable, AVGO needs to broaden its customer base and order book to restore growth and confidence.

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Related Dolphin Research on AVGO (AVGO.O):

Earnings calls:

Jun 4, 2026 transcript: AVGO (Trans): 'We only sell chips'; customers like GOOGL are diversifying supply

Jun 4, 2026 earnings take: AVGO: Titans vs. Titans — is the ASIC camp splitting?

Mar 5, 2026 transcript: AVGO (Trans): FY2027 AI revenue to top $100 bn; XPU partnerships remain sustainable

Mar 5, 2026 earnings take: AVGO: AI in full swing — a stronger rival to NVDA?

Risk disclosure and disclaimer: Dolphin Research Disclaimer and General Disclosure