Huachuang Securities: Surge in AI computing power demand accelerates growth of advanced packaging industry

According to the Zhitong Finance APP, Huachuang Securities released a research report stating that the rapid development of high-computing scenarios such as AI servers and smart vehicles is driving the expansion of the advanced packaging market, with continued growth in demand for Chiplet, 2.5D/3D and other high-integration packaging. The progress of domestic substitution in the semiconductor industry chain is accelerating, and domestic platform manufacturers are entering a window period. It is recommended to pay attention to companies such as JCET (600584.SH), TFME (002156.SZ), and WLCSP (603005.SH), which have advanced process platform capabilities and significant progress in customer resource introduction.

The main points of Huachuang Securities are as follows:

Beyond the limits of Moore's Law, advanced packaging has become one of the key technologies in the high prosperity computing cycle

High-performance scenarios such as AI, large models, and data centers are rapidly evolving, facing three bottlenecks: "power wall, memory wall, cost wall" in terms of chip bandwidth, power consumption, and integration density, making it difficult for traditional processes to support performance leaps. Advanced packaging, with its capabilities of miniaturization, high density, low power consumption, and heterogeneous integration, is moving from the back end of manufacturing to the front end of system design. Global leading players are intensifying their layout in advanced packaging technology, with TSMC continuing to expand CoWoS production, and Intel and Samsung increasing investment in Foveros and X-Cube technology platforms, highlighting the importance of advanced packaging in the computing era.

The development of AI and intelligent driving drives the continuous expansion of the advanced packaging market, with Chiplet and 2.5D/3D packaging accelerating penetration

According to Yole statistics, the global advanced packaging market is expected to reach USD 45 billion in 2024, accounting for over 55% of the overall packaging market, and is expected to rise to USD 80 billion by 2030, with a CAGR of 9.4% from 2024 to 2030. From the perspective of downstream applications, AI servers have extreme requirements for high-bandwidth storage and high-speed interconnects, with HBM+CoWoS combinations becoming standard; the intelligentization of vehicles is driving the complexity of automotive SoCs, coupled with the recovery of the consumer electronics cycle, supporting the continuous growth of the advanced packaging market. From the perspective of technological upgrades, as the computing density of application scenarios continues to rise, packaging forms are accelerating towards high-integration solutions such as Chiplet architecture, 2.5D interposers, and 3D stacking. According to Yole's forecast, the proportion of 2.5D/3D packaging will increase from 27% in 2023 to 40% in 2029, with a compound annual growth rate of 18.05%, far exceeding the industry average growth rate.

Domestic advanced packaging has great potential, with high growth in demand and opportunities for domestic substitution resonance

According to data from Ruiguan Industrial Research Institute, China's advanced packaging market continues to grow rapidly, with the market size expected to reach RMB 69.8 billion in 2024, and a compound annual growth rate of 18.7% from 2020 to 2024; however, the penetration rate is only 40%, still below the global average level of 55%, indicating significant room for improvement in the medium to long term. As the domestic chip design industry continues to evolve, the iterative momentum of domestic packaging platforms is accelerating. Meanwhile, leading manufacturers such as TSMC are experiencing tight production capacity and extended production cycles, with resources further concentrating on top customers in AI, creating a window for domestic platforms to introduce and validate orders for some mid-to-long tail orders. At the same time, the process of domestic substitution in the semiconductor industry chain is accelerating, with policies and capital collaborating to support the construction of advanced packaging platforms, positioning domestic platform manufacturers at a strategic starting point for breakthroughs in high-end processes and market share enhancement TSMC Leads AI Packaging Ecosystem with CoWoS, Mainland Manufacturers Accelerate Layout to Break Through

The global advanced packaging market presents a pattern of one strong player and many strong competitors. TSMC builds the 3DFabric platform through CoWoS, InFO, and SoIC, comprehensively covering the heterogeneous integration needs from mobile terminals to high-performance computing, firmly occupying the high ground of AI computing power packaging. CoWoS, with its first-mover advantage, has bound AI chip customers such as NVIDIA, forming strong customer stickiness and becoming the mainstream solution for AI acceleration chip packaging. Intel strengthens its high-performance product packaging capabilities under its own IDM system relying on the EMIB+Foveros parallel architecture; Samsung continues to invest in the 2.5D/3D direction through I-Cube and X-Cube, focusing on breaking through key bottlenecks such as hybrid bonding. Mainland manufacturers are also evolving simultaneously: 1) JCET has the most comprehensive layout, covering WLCSP, Fan-Out, and 2.5D/3D directions, having achieved industrialization of wafer-level packaging platforms and holding a leading position domestically; 2) TFME actively collaborates with international clients such as AMD to promote Chiplet and 2.5D platform construction, enhancing process synergy capabilities and product complexity, gradually extending towards mid-to-high-end heterogeneous integration; 3) Huatian Technology builds the "HMatrix" advanced packaging platform system, striving to benchmark against CoWoS in the key technology direction of eSinC; Yongxi Electronics is also actively promoting Fan-out and 2.5D/3D layouts; Shenghe Jingwei and WLCSP focus on mid-range silicon interconnection and sensor TSV packaging paths, achieving technological validation and scaling breakthroughs in niche tracks.

Risk Warning: Risks of changes in the external trade environment; risks of fluctuations in downstream prosperity; risks of technical thresholds and process yield