<div id="readability-page-1">China’s chip design software industry is rallying behind Huawei Technologies’ ambitious new architecture aimed at producing chips that can rival leading global products, but analysts warn a steep uphill climb remains before local players can break the market stranglehold of US rivals. Empyrean Technology, a major Chinese electronic design automation (EDA) provider, became the latest supporter of the new chipmaking methodology. The company recently unveiled Argus, a new physical verification platform for three-dimensional integrated circuit (3D IC) design, integrated into its expanding suite of tools. It described 3D IC technology as “a key carrier” for implementing Huawei’s “Tau Scaling Law”. The announcement followed a claimed breakthrough by researchers at Peking University, who unveiled a prototype EDA tool using a “true-3D” approach, said to be compatible with Huawei’s LogicFolding architecture. That milestone came just one day after Huawei introduced its Tau Scaling framework late last month. Presented as an alternative to Moore’s Law, the Tau Scaling Law shifts the focus of chip development from shrinking transistors to compressing signal travel time across a system. By stacking flat circuits vertically into 3D structures through “LogicFolding”, the approach aims to match the transistor density and performance of leading-edge chips without relying on advanced Western lithography equipment restricted by US sanctions.  The string of developments underscores how China’s semiconductor industry is rushing to adapt to Huawei’s paradigm shift. Supporting the new architecture requires specialised EDA tools capable of handling new, complex mathematical models for silicon behaviour. Yet serious questions remain over whether these nascent tools can be immediately integrated into commercial workflows. Industry insiders said China’s domestic EDA toolkits remained a weak link in its broader semiconductor self-sufficiency drive. “Whether China can develop its own supporting EDA design and simulation tools is a very difficult thing to crack for the adoption of Tau Scaling Law,” said Han Chaoyang, vice-president of marketing at Chinese artificial intelligence chip company ListenAI. Such development would require not only Huawei’s breakthrough, but coordinated efforts across the domestic chip supply chain, he added. “Traditional EDA is designed for [two-dimensional] planar routing, while 3D folding requires multi-layer layout and routing, cross-layer timing convergence, and cross-layer power integrity analysis,” Chinese semiconductor research firm ICwise said in a research note in late May. Domestic and international researchers were still catching up on this area, it added. ICwise expected the step to take at least four or five years of engineering implementation. Still, analysts believed major domestic EDA providers would benefit from opportunities brought by Huawei’s ambitious target of achieving 1.4 nanometre-equivalent chips by 2031.  Domestic EDA was projected to move from “filling the gaps with overseas tools” to “collaborative innovation” oriented towards domestic processes, architectures and systems, said Wu Mingyuan, an analyst at Huachuang Securities, in a research note in late May. Vendors with capabilities in process collaboration, manufacturing data closed-loop systems, and customer ecosystem positioning are expected to benefit first, Wu said, highlighting Empyrean Technology, Primarius Technologies and Semitronix – the three listed domestic EDA providers – as among the biggest beneficiaries. Despite the optimism surrounding the Tau Scaling advancements, the three firms still operate largely in the shadow of US-based technology firms Synopsys, Cadence Design Systems and Siemens EDA. “China cannot build competitive EDA tools because software complexity has no physical ceiling,” research firm SemiAnalysis said in a recent report, adding that Chinese vendors were more likely to “stabilise at US$500 million to US$1 billion in revenue serving China’s mature-node market”. Currently, local tools can mostly handle isolated aspects, but the primary hurdle is the lack of a domestic “full-flow” digital solution. In contrast, Synopsys and Cadence offer end-to-end, integrated ecosystems. Still, SemiAnalysis data showed domestic companies had gained a larger global share in recent years amid Beijing’s push for chip self-sufficiency. China’s EDA revenue rose from 2018 to 2024, with its global market share rising from 0.9 per cent to 5.3 per cent, according to SemiAnalysis. The three publicly traded Chinese EDA vendors together generated US$308 million in 2024, accounting for around 1.8 per cent of the global market, it added.</div>

CDNS

301269

SNPS

SNPX

<p>China's chip design software industry is rallying behind Huawei’s new 'Tau Scaling Law' architecture, which uses 3D integration to bypass US sanctions. While firms like Empyrean Technology are developing supporting EDA tools, analysts warn of significant technical hurdles and a multi-year gap before domestic solutions can rival US giants like Synopsys and Cadence. Despite these challenges, Chinese EDA providers are expected to benefit from increased demand for collaborative innovation, with their global market share rising steadily.</p>

SCMP

Cadence Design

EMPYREAN

Synopsys

Tradr 2X Long SNPS Daily ETF

Polaris

PRIMARIUS

SEMITRONIX

Siemens AG

Siemens

Can Huawei’s breakthrough help China’s chip  design software firms catch US rivals?