<p>/PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO)（&#34;HOLO&#34;或&#34;公司&#34;）是一家技術服務提供商，提出了一種創新的硬件加速技術，將量子張量網絡算法轉換為可以在現場可編程門陣列（FPGA）上運行的並行計算電路，實現了在經典硬件上高效的量子自旋模型模擬。這一成就為量子物理研究、量子算法驗證以及未來量子設備的數字雙胞胎模擬提供了一條全新的工程路徑。</p>
<p>在量子多體系統的研究中，張量網絡（TN）算法是一種極為高效的數值工具。它通過將高維量子態分解為多個低維張量的網絡結構，在一定程度上克服了指數狀態空間擴展的問題。典型的張量網絡模型包括矩陣乘積態（MPS）、投影糾纏對態（PEPS）和多尺度糾纏重整化（MERA）等。這些算法在凝聚態物理、量子相變、量子自旋模型模擬等方面發揮着基礎性作用。</p>
<p>然而，當我們希望提高系統表徵的精度並引入更高的糾纏自由度時，張量的維度和連接性急劇增長，導致計算複雜性迅速從多項式級別跨越到指數級別。以二維自旋系統為例，當糾纏秩從χ=8 擴展到χ=32 時，每次迭代的浮點運算次數幾乎增加了百倍，存儲帶寬和內存訪問延遲成為瓶頸。這種指數爆炸特性使得即使是高端 CPU 和 GPU 平台也難以在合理的時間內完成模擬任務。</p>
<p>為此，HOLO 嘗試突破傳統處理器架構的限制，探索在硬件層面上算法重構和邏輯映射的可行路徑。現場可編程門陣列（FPGA）憑藉其可重構性、並行性和低延遲特性，為張量網絡計算提供了新的可能性。通過將核心計算模塊（如張量收縮、張量展開、矩陣乘法 - 加法操作等）直接映射到硬件電路的邏輯層面，可以大幅減少內存訪問消耗和控制開銷，實現深度流水線的高密度並行計算。</p>
<p>HOLO 技術的核心在於算法 - 硬件協同設計，將張量網絡算法從軟件邏輯層面剖析為可以直接硬件化的計算單元，並以 FPGA 為載體構建高密度並行可擴展架構。</p>
<p>首先，對量子自旋模型的張量網絡結構進行了系統分析。以海森堡自旋鏈和二維伊辛模型為代表的典型系統，其哈密頓量可分解為局部相互作用項，通過張量網絡編碼為多個局部張量。每個張量節點的收縮本質上對應於張量乘積、矩陣乘法和求和操作。傳統的 CPU 計算依賴於通用指令集的順序執行，而 GPU 雖然具有大規模並行性，但受限於內存訪問延遲和內核調度，難以實現針對性的優化。FPGA 架構允許在硬件層面直接定義這些計算邏輯，消除冗餘調度環節，使數據能夠在片上高速緩存中以流水線方式連續流動。</p>
<p>在實現過程中，HOLO 構建了一個分層張量收縮流水線。該流水線包括三個主要層級：</p>
<p>輸入和調度層：負責將高維張量分解為多個可管理的塊結構，並進行數據流調度和依賴分析。</p>
<p>核心計算層：由多個 MAC 陣列組成，支持任意維度的張量收縮操作。每個計算單元採用定製邏輯，實現浮點加法和乘法的流水線級並行。</p>
<p>輸出和歸約層：執行張量結果的合併、歸一化和中間狀態緩存，為後續迭代提供輸入。</p>
<p>在硬件邏輯設計中，通過 Verilog 和高級綜合（HLS）工具的結合方法，自動生成張量操作電路，並針對不同的張量連接圖採用多分區策略。通過靜態調度和數據重用機制，計算單元在片上形成高密度並行陣列，在有限的邏輯資源下實現最大計算吞吐率。</p>
<p>該技術以 FPGA 為核心硬件平台，提出並實現了一種加速量子張量網絡計算的並行化硬件架構。通過算法結構重構、邏輯電路映射、流水線設計和混合精度優化，HOLO 成功將複雜的張量網絡計算任務轉化為高效的 FPGA 邏輯操作，實現了比 CPU 快 1.7 倍的性能突破，能效提高超過 2 倍。這項技術不僅展示了 FPGA 在量子模擬中的潛力，還為量子算法硬件實現和可重構量子加速器設計提供了實際基礎。</p>
<p>未來，HOLO 將繼續沿着從算法到電路的設計理念，推動更多量子計算核心模塊的硬件實現，包括量子變分算法（VQE）、量子線性系統求解器（QLSA）以及量子機器學習模型的 FPGA 化，以構建完整的量子算法加速生態系統。相信通過在這一方向的持續研究，FPGA 將成為量子計算與經典計算之間的重要橋樑，為量子技術的產業化發展提供堅實的技術支持。</p>
<p>關於 MicroCloud Hologram Inc.</p>
<p>MicroCloud Hologram Inc.（納斯達克：HOLO）致力於全息技術的研發和應用。其全息技術服務包括基於全息技術的全息光檢測與測距（LiDAR）解決方案、全息 LiDAR 點雲算法架構設計、技術全息成像解決方案、全息 LiDAR 傳感器芯片設計以及全息車輛智能視覺技術，為提供全息高級駕駛輔助系統（ADAS）的客户提供服務。MicroCloud Hologram Inc.為全球客户提供全息技術服務。MicroCloud Hologram Inc.還提供全息數字雙胞胎技術服務，並擁有專有的全息數字雙胞胎技術資源庫。其全息數字雙胞胎技術資源庫結合了全息數字雙胞胎軟件、數字內容、空間數據驅動的數據科學、全息數字雲算法和全息 3D 捕捉技術，以 3D 全息形式捕捉形狀和物體。MicroCloud Hologram Inc.專注於量子計算和量子全息等領域的發展，現金儲備超過 30 億元人民幣，並計劃從現金儲備中投資超過 4 億美元，參與區塊鏈開發、量子計算技術開發、量子全息技術開發以及人工智能 AR 等前沿技術領域的衍生品和技術開發。MicroCloud Hologram Inc.的目標是成為全球領先的量子全息和量子計算技術公司。</p>
<p>安全港聲明</p>
<p>本新聞稿包含根據 1995 年《私人證券訴訟改革法案》定義的前瞻性陳述。前瞻性陳述包括有關計劃、目標、策略、未來事件或表現及其基本假設的陳述，以及其他非歷史事實的陳述。當公司使用諸如 “可能”、“將”、“打算”、“應該”、“相信”、“期望”、“預期”、“項目”、“估計” 或類似表達時，這些表達並不單純與歷史事項相關，而是在進行前瞻性陳述。前瞻性陳述並不保證未來的表現，並涉及可能導致實際結果與公司在前瞻性陳述中討論的預期存在重大差異的風險和不確定性。這些陳述受到不確定性和風險的影響，包括但不限於以下內容：公司的目標和策略；公司的未來業務發展；產品和服務的需求和接受度；技術變化；經濟狀況；聲譽和品牌；競爭和定價的影響；政府法規；一般經濟波動；財務狀況和經營結果；全息行業的預期增長以及公司計劃服務的中國和國際市場的商業條件，以及與上述任何內容相關的假設和公司向證券交易委員會（“SEC”）提交的報告中包含的其他風險，包括公司最近提交的 10-K 表格年度報告和 6-K 表格當前報告及其後續提交的文件。因此，投資者被提醒不要對本新聞稿中的任何前瞻性陳述過度依賴。其他因素在公司向 SEC 提交的文件中進行了討論，這些文件可在 www.sec.gov 上查閲。公司沒有義務公開修訂這些前瞻性陳述，以反映本日期後發生的事件或情況。</p>
<p>來源：MicroCloud Hologram Inc.</p>

HOLO

<p>MicroCloud Hologram Inc.（納斯達克代碼：HOLO）推出了一種利用現場可編程門陣列（FPGA）的硬件加速技術，以增強量子張量網絡計算。這項創新使得在經典硬件上高效模擬量子自旋模型成為可能，解決了量子多體系統中計算複雜性的問題。通過將核心計算任務直接映射到硬件電路中，HOLO 的技術在性能上比 CPU 提高了 1.7 倍，並且將能效翻倍。該公司旨在進一步開發量子計算模塊，包括量子變分算法和量子機器學習模型</p>

<p>, /PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO), (&#34;HOLO&#34; or the &#34;Company&#34;), a technology service provider, proposed an innovative hardware acceleration technology that converts the quantum tensor network algorithm into parallel computing circuits that can run on field programmable gate arrays (FPGA), achieving efficient quantum spin model simulation on classical hardware. This achievement provides a brand-new engineered path for quantum physics research, quantum algorithm verification, and digital twin simulation of future quantum devices.</p>
<div class="lb-trans"><p>/PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO)（&#34;HOLO&#34;或&#34;公司&#34;）是一家技術服務提供商，提出了一種創新的硬件加速技術，將量子張量網絡算法轉換為可以在現場可編程門陣列（FPGA）上運行的並行計算電路，實現了在經典硬件上高效的量子自旋模型模擬。這一成就為量子物理研究、量子算法驗證以及未來量子設備的數字雙胞胎模擬提供了一條全新的工程路徑。</p>
</div><p>In the research of quantum many-body systems, the tensor network (TN) algorithm is an extremely efficient numerical tool. It overcomes the problem of exponential state space expansion to a certain extent by decomposing high-dimensional quantum states into a network structure of multiple low-dimensional tensors. Typical tensor network models include matrix product states (MPS), projected entangled pair states (PEPS), and multi-scale entanglement renormalization (MERA), etc. These algorithms play a foundational role in condensed matter physics, quantum phase transitions, quantum spin model simulations, and other aspects.</p>
<div class="lb-trans"><p>在量子多體系統的研究中，張量網絡（TN）算法是一種極為高效的數值工具。它通過將高維量子態分解為多個低維張量的網絡結構，在一定程度上克服了指數狀態空間擴展的問題。典型的張量網絡模型包括矩陣乘積態（MPS）、投影糾纏對態（PEPS）和多尺度糾纏重整化（MERA）等。這些算法在凝聚態物理、量子相變、量子自旋模型模擬等方面發揮着基礎性作用。</p>
</div><p>However, when we hope to improve the precision of system characterization and introduce higher entanglement degrees of freedom, the dimensions and connectivity of tensors grow sharply, causing the computational complexity to rapidly cross from polynomial to exponential levels. Taking a two-dimensional spin system as an example, when the entanglement rank expands from χ=8 to χ=32, the floating-point operations per iteration increase nearly a hundredfold, and storage bandwidth and memory access latency become bottlenecks. This exponential explosion characteristic makes it difficult even for high-end CPU and GPU platforms to complete simulation tasks within a reasonable time.</p>
<div class="lb-trans"><p>然而，當我們希望提高系統表徵的精度並引入更高的糾纏自由度時，張量的維度和連接性急劇增長，導致計算複雜性迅速從多項式級別跨越到指數級別。以二維自旋系統為例，當糾纏秩從χ=8 擴展到χ=32 時，每次迭代的浮點運算次數幾乎增加了百倍，存儲帶寬和內存訪問延遲成為瓶頸。這種指數爆炸特性使得即使是高端 CPU 和 GPU 平台也難以在合理的時間內完成模擬任務。</p>
</div><p>To this end, HOLO attempts to break out of the limitations of traditional processor architectures and explore feasible paths for algorithm reconstruction and logic mapping at the hardware level. Field programmable gate arrays (FPGA), with their reconfigurability, parallelism, and low-latency characteristics, provide new possibilities for tensor network computations. By directly mapping core computational modules (such as tensor contraction, tensor unfolding, matrix multiplication-addition operations, etc.) into hardware circuits at the logic level, it can greatly reduce memory access consumption and control overhead, achieving deep pipelined high-density parallel computing.</p>
<div class="lb-trans"><p>為此，HOLO 嘗試突破傳統處理器架構的限制，探索在硬件層面上算法重構和邏輯映射的可行路徑。現場可編程門陣列（FPGA）憑藉其可重構性、並行性和低延遲特性，為張量網絡計算提供了新的可能性。通過將核心計算模塊（如張量收縮、張量展開、矩陣乘法 - 加法操作等）直接映射到硬件電路的邏輯層面，可以大幅減少內存訪問消耗和控制開銷，實現深度流水線的高密度並行計算。</p>
</div><p>The core of HOLO's technology lies in algorithm-hardware co-design, which dissects the tensor network algorithm from the software logic level into computational units that can be directly hardware-ized, and builds a high-density parallel scalable architecture with FPGA as the carrier.</p>
<div class="lb-trans"><p>HOLO 技術的核心在於算法 - 硬件協同設計，將張量網絡算法從軟件邏輯層面剖析為可以直接硬件化的計算單元，並以 FPGA 為載體構建高密度並行可擴展架構。</p>
</div><p>First, a systematic analysis was performed on the tensor network structure of quantum spin models. Typical systems represented by the Heisenberg spin chain and the two-dimensional Ising model have their Hamiltonians decomposable into local interaction terms, encoded into several local tensors through tensor networks. The contraction of each tensor node essentially corresponds to tensor product, matrix multiplication, and summation operations. Traditional CPU computations rely on sequential execution of general instruction sets, while GPUs, although possessing large-scale parallelism, are limited by memory access latency and kernel scheduling, making it difficult to achieve targeted optimization. The FPGA architecture allows direct definition of these computational logics at the hardware level, eliminating redundant scheduling links, enabling data to flow continuously in a pipeline manner in the on-chip high-speed cache.</p>
<div class="lb-trans"><p>首先，對量子自旋模型的張量網絡結構進行了系統分析。以海森堡自旋鏈和二維伊辛模型為代表的典型系統，其哈密頓量可分解為局部相互作用項，通過張量網絡編碼為多個局部張量。每個張量節點的收縮本質上對應於張量乘積、矩陣乘法和求和操作。傳統的 CPU 計算依賴於通用指令集的順序執行，而 GPU 雖然具有大規模並行性，但受限於內存訪問延遲和內核調度，難以實現針對性的優化。FPGA 架構允許在硬件層面直接定義這些計算邏輯，消除冗餘調度環節，使數據能夠在片上高速緩存中以流水線方式連續流動。</p>
</div><p>In the implementation, HOLO constructed a Hierarchical Tensor Contraction Pipeline. This pipeline includes three main levels:</p>
<div class="lb-trans"><p>在實現過程中，HOLO 構建了一個分層張量收縮流水線。該流水線包括三個主要層級：</p>
</div><p>Input and scheduling layer: responsible for decomposing high-dimensional tensors into several manageable block structures, and performing data flow scheduling and dependency analysis.</p>
<div class="lb-trans"><p>輸入和調度層：負責將高維張量分解為多個可管理的塊結構，並進行數據流調度和依賴分析。</p>
</div><p>Core computing layer: composed of multiple MAC Array, supporting tensor contraction operations of arbitrary dimensions. Each computing unit adopts customized logic to achieve pipeline-level parallelism for floating-point addition and multiplication.</p>
<div class="lb-trans"><p>核心計算層：由多個 MAC 陣列組成，支持任意維度的張量收縮操作。每個計算單元採用定製邏輯，實現浮點加法和乘法的流水線級並行。</p>
</div><p>Output and reduction layer: executes the merging, normalization, and intermediate state caching of tensor results, providing input for subsequent iterations.</p>
<div class="lb-trans"><p>輸出和歸約層：執行張量結果的合併、歸一化和中間狀態緩存，為後續迭代提供輸入。</p>
</div><p>In the hardware logic design, through the combined method of Verilog and high-level synthesis (HLS) tools, tensor operation circuits are automatically generated, and multi-partition strategies are adopted for different tensor connectivity graphs. Through static scheduling and data reuse mechanisms, the computing units form a high-density parallel array on-chip, achieving the maximum computational throughput rate under limited logic resources.</p>
<div class="lb-trans"><p>在硬件邏輯設計中，通過 Verilog 和高級綜合（HLS）工具的結合方法，自動生成張量操作電路，並針對不同的張量連接圖採用多分區策略。通過靜態調度和數據重用機制，計算單元在片上形成高密度並行陣列，在有限的邏輯資源下實現最大計算吞吐率。</p>
</div><p>This technology takes FPGA as the core hardware platform, proposing and implementing a parallelized hardware architecture for accelerating quantum tensor network computations. Through algorithm structure reconstruction, logic circuit mapping, pipelined design, and mixed-precision optimization, HOLO successfully transforms complex tensor network computational tasks into efficient FPGA logic operations, achieving a performance breakthrough that is 1.7 times faster than CPU and with energy efficiency improved by more than 2 times. This technology not only demonstrates the potential of FPGA in quantum simulation but also provides practical basis for quantum algorithm hardware implementation and reconfigurable quantum accelerator design.</p>
<div class="lb-trans"><p>該技術以 FPGA 為核心硬件平台，提出並實現了一種加速量子張量網絡計算的並行化硬件架構。通過算法結構重構、邏輯電路映射、流水線設計和混合精度優化，HOLO 成功將複雜的張量網絡計算任務轉化為高效的 FPGA 邏輯操作，實現了比 CPU 快 1.7 倍的性能突破，能效提高超過 2 倍。這項技術不僅展示了 FPGA 在量子模擬中的潛力，還為量子算法硬件實現和可重構量子加速器設計提供了實際基礎。</p>
</div><p>In the future, HOLO will continue along the design philosophy from algorithm to circuit, promoting the hardware implementation of more quantum computing core modules, including quantum variational algorithms (VQE), quantum linear system solvers (QLSA), and FPGA-ization of quantum machine learning models, to build a complete quantum algorithm acceleration ecosystem. It is believed that, through continuous research in this direction, FPGA will become an important bridge between quantum computing and classical computing, providing solid technical support for the industrialization development of quantum technology.</p>
<div class="lb-trans"><p>未來，HOLO 將繼續沿着從算法到電路的設計理念，推動更多量子計算核心模塊的硬件實現，包括量子變分算法（VQE）、量子線性系統求解器（QLSA）以及量子機器學習模型的 FPGA 化，以構建完整的量子算法加速生態系統。相信通過在這一方向的持續研究，FPGA 將成為量子計算與經典計算之間的重要橋樑，為量子技術的產業化發展提供堅實的技術支持。</p>
</div><p>About MicroCloud Hologram Inc.</p>
<div class="lb-trans"><p>關於 MicroCloud Hologram Inc.</p>
</div><p>MicroCloud Hologram Inc. (NASDAQ: HOLO) is committed to the research and development and application of holographic technology. Its holographic technology services include holographic light detection and ranging (LiDAR) solutions based on holographic technology, holographic LiDAR point cloud algorithm architecture design, technical holographic imaging solutions, holographic LiDAR sensor chip design, and holographic vehicle intelligent vision technology, providing services to customers offering holographic advanced driving assistance systems (ADAS). MicroCloud Hologram Inc. provides holographic technology services to global customers. MicroCloud Hologram Inc. also provides holographic digital twin technology services and owns proprietary holographic digital twin technology resource libraries. Its holographic digital twin technology resource library utilizes a combination of holographic digital twin software, digital content, space data-driven data science, holographic digital cloud algorithms, and holographic 3D capture technology to capture shapes and objects in 3D holographic form. MicroCloud Hologram Inc. focuses on developments such as quantum computing and quantum holography, with cash reserves exceeding 3 billion RMB, and plans to invest more than 400 million in USD from the cash reserves to engage in blockchain development, quantum computing technology development, quantum holography technology development, and derivatives and technology development in frontier technology fields such as artificial intelligence AR. MicroCloud Hologram Inc.'s goal is to become a global leading quantum holography and quantum computing technology company.</p>
<div class="lb-trans"><p>MicroCloud Hologram Inc.（納斯達克：HOLO）致力於全息技術的研發和應用。其全息技術服務包括基於全息技術的全息光檢測與測距（LiDAR）解決方案、全息 LiDAR 點雲算法架構設計、技術全息成像解決方案、全息 LiDAR 傳感器芯片設計以及全息車輛智能視覺技術，為提供全息高級駕駛輔助系統（ADAS）的客户提供服務。MicroCloud Hologram Inc.為全球客户提供全息技術服務。MicroCloud Hologram Inc.還提供全息數字雙胞胎技術服務，並擁有專有的全息數字雙胞胎技術資源庫。其全息數字雙胞胎技術資源庫結合了全息數字雙胞胎軟件、數字內容、空間數據驅動的數據科學、全息數字雲算法和全息 3D 捕捉技術，以 3D 全息形式捕捉形狀和物體。MicroCloud Hologram Inc.專注於量子計算和量子全息等領域的發展，現金儲備超過 30 億元人民幣，並計劃從現金儲備中投資超過 4 億美元，參與區塊鏈開發、量子計算技術開發、量子全息技術開發以及人工智能 AR 等前沿技術領域的衍生品和技術開發。MicroCloud Hologram Inc.的目標是成為全球領先的量子全息和量子計算技術公司。</p>
</div><p>Safe Harbor Statement</p>
<div class="lb-trans"><p>安全港聲明</p>
</div><p>This press release contains forward-looking statements as defined by the Private Securities Litigation Reform Act of 1995. Forward-looking statements include statements concerning plans, objectives, goals, strategies, future events or performance, and underlying assumptions and other statements that are other than statements of historical facts. When the Company uses words such as &#34;may,&#34; &#34;will,&#34; &#34;intend,&#34; &#34;should,&#34; &#34;believe,&#34; &#34;expect,&#34; &#34;anticipate,&#34; &#34;project,&#34; &#34;estimate,&#34; or similar expressions that do not relate solely to historical matters, it is making forward-looking statements. Forward-looking statements are not guarantees of future performance and involve risks and uncertainties that may cause the actual results to differ materially from the Company's expectations discussed in the forward-looking statements. These statements are subject to uncertainties and risks including, but not limited to, the following: the Company's goals and strategies; the Company's future business development; product and service demand and acceptance; changes in technology; economic conditions; reputation and brand; the impact of competition and pricing; government regulations; fluctuations in general economic; financial condition and results of operations; the expected growth of the holographic industry and business conditions in China and the international markets the Company plans to serve and assumptions underlying or related to any of the foregoing and other risks contained in reports filed by the Company with the Securities and Exchange Commission (&#34;SEC&#34;), including the Company's most recently filed Annual Report on Form 10-K and current report on Form 6-K and its subsequent filings. For these reasons, among others, investors are cautioned not to place undue reliance upon any forward-looking statements in this press release. Additional factors are discussed in the Company's filings with the SEC, which are available for review at www.sec.gov. The Company undertakes no obligation to publicly revise these forward-looking statements to reflect events or circumstances that arise after the date hereof.</p>
<div class="lb-trans"><p>本新聞稿包含根據 1995 年《私人證券訴訟改革法案》定義的前瞻性陳述。前瞻性陳述包括有關計劃、目標、策略、未來事件或表現及其基本假設的陳述，以及其他非歷史事實的陳述。當公司使用諸如 “可能”、“將”、“打算”、“應該”、“相信”、“期望”、“預期”、“項目”、“估計” 或類似表達時，這些表達並不單純與歷史事項相關，而是在進行前瞻性陳述。前瞻性陳述並不保證未來的表現，並涉及可能導致實際結果與公司在前瞻性陳述中討論的預期存在重大差異的風險和不確定性。這些陳述受到不確定性和風險的影響，包括但不限於以下內容：公司的目標和策略；公司的未來業務發展；產品和服務的需求和接受度；技術變化；經濟狀況；聲譽和品牌；競爭和定價的影響；政府法規；一般經濟波動；財務狀況和經營結果；全息行業的預期增長以及公司計劃服務的中國和國際市場的商業條件，以及與上述任何內容相關的假設和公司向證券交易委員會（“SEC”）提交的報告中包含的其他風險，包括公司最近提交的 10-K 表格年度報告和 6-K 表格當前報告及其後續提交的文件。因此，投資者被提醒不要對本新聞稿中的任何前瞻性陳述過度依賴。其他因素在公司向 SEC 提交的文件中進行了討論，這些文件可在 www.sec.gov 上查閲。公司沒有義務公開修訂這些前瞻性陳述，以反映本日期後發生的事件或情況。</p>
</div><p>SOURCE MicroCloud Hologram Inc.</p>
<div class="lb-trans"><p>來源：MicroCloud Hologram Inc.</p>
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MicroCloud Hologram Inc. 利用 FPGA 加速張量網絡計算以實現量子自旋模型 | HOLO 股票新聞