The United States is accelerating its efforts in the competition for global chip manufacturing dominance. On January 16, 2025, the U.S. Department of Commerce announced that the CHIPS National Advanced Packaging Manufacturing Program (NAPMP) has allocated $1.4 billion in incentive funding to strengthen the U.S. leadership in advanced packaging and to validate and scale new technologies for U.S. manufacturing. The U.S. investment in advanced packaging technology reflects its high regard for the future development of the semiconductor industry.
The pace of miniaturization expressed by Moore's Law can no longer further enhance the performance of microelectronics technology. Today, advanced packaging is not just the &#34;last mile&#34; of chip manufacturing; it is crucial for improving chip performance, reducing costs, and supporting more complex system integration (such as AI, 5G, and high-performance computing). In particular, the issue of chip heat dissipation has become one of the major challenges that manufacturers urgently need to address. Since the 1950s, packaging technology has been used to alleviate heat, provide protection, and ensure current flow; however, as chip performance continues to improve, the challenges faced by packaging technology have become increasingly complex.
The U.S. vision for advanced packaging states that without investment in advanced packaging, semiconductor investments will not succeed. So, what key technologies does the U.S. favor for advanced packaging? We can glean some insights from the initial beneficiaries.
Where will the $1.4 billion go?
First, according to the first Notice of Funding Opportunity (NOFO) from CHIPS NAPMP, a total of $300 million in direct cash grants will be provided to SK subsidiary Absolics Inc., Applied Materials Inc., and Arizona State University, with each receiving $100 million for advanced substrate and materials research. This funding injection in this area reflects the U.S. concern over the current bottlenecks in semiconductor packaging technology. Substrates and materials are the core of packaging technology, determining the performance, stability, and manufacturability of chips.
Substrates
In the field of glass substrates, companies such as Intel, AMD, Samsung, LG Innotek, and SKC's U.S. subsidiary Absolics are actively focusing on this technology. Glass substrates are a physical platform that allows multiple semiconductor chips to be seamlessly assembled together, enabling high-bandwidth communication between chips, efficient power transmission, and dissipation of unnecessary heat.
Intel has stated that glass substrates will provide the foundation for integrating one trillion transistors in a single package over the next decade. Given its enormous potential, there have been recent rumors that Intel plans to achieve mass production of glass substrates as early as 2026. Intel has invested nearly a decade in this field and has established a complete glass research production line in Arizona, investing over $1 billion. To complete this ecosystem, Intel also needs to work closely with equipment and material partners. Currently, only a few companies can afford such investments, and Intel appears to be the only company that has successfully developed glass substrates
Advanced packaging achieved through advanced substrates can enable high-performance computing for AI, next-generation wireless communication, and more efficient power electronics. Such substrates are not yet produced in the United States but are crucial for establishing and expanding domestic advanced packaging capabilities.
The U.S. Department of Commerce has provided $100 million in funding to Absolics to accelerate domestic research and development (R&amp;D) of glass core substrates. Absolics is building a 120,000 square foot advanced small-batch manufacturing facility in Covington, Georgia, and this funding will help establish a critical domestic supply chain around the facility. Additionally, last month, Absolics also received $75 million in manufacturing subsidies to further support its R&amp;D and production capabilities.
Meanwhile, the Department of Commerce has also provided $100 million in funding to Applied Materials to support the development and promotion of disruptive silicon core substrate technology, advancing next-generation packaging technology and 3D heterogeneous integration. The project will validate its feasibility through key packaging technology demonstrations and promote its implementation in practical applications.
Fan-Out Wafer-Level Packaging (FOWLP) Technology
The third recipient of the funding—Arizona State University (ASU)—is one of the few universities in the U.S. teaching advanced packaging to students. ASU has established collaborations with local advanced packaging companies such as Deca Technologies and NXP in the field of packaging technology. The university is training a skilled workforce urgently needed in the semiconductor industry.
This time, Arizona State University's $100 million funding will focus on developing and validating new packaging technologies, particularly Fan-Out Wafer-Level Packaging (FOWLP). The project centers around ASU's Advanced Electronics and Photonics Core Facility and supports ASU in exploring the commercial viability of 300mm wafer-level and 600mm panel-level manufacturing, a technology that currently lacks commercial capability in the U.S.
According to Tim Olson, founder of Deca Technologies, a partner of Arizona State University, fan-out wafer-level packaging is very unique; at the highest level, the fan-out packaging part is akin to 'glue.' You can bond together whatever you want to assemble, whether it's processor chips, memory chips, memory chip combinations, RF (radio frequency) communication chips, or batteries. No other packaging technology allows you to bond these things together in any direction and orientation as it does.
<img src="https://imageproxy.pbkrs.com/http://img.zhitongcaijing.com/images/contentformat/16d2447d83e0f5828294ccff2c6f9775.jpg?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/http://img.zhitongcaijing.com/images/contentformat/16d2447d83e0f5828294ccff2c6f9775.jpg"/>
Different types of packaging technologies are suitable for different applications.
(Source: ASU)
The ASU team consists of more than 10 partners, led by industry pioneer Deca Technologies, centered around a regional hub for microelectronics manufacturing, comprising businesses of all sizes, universities, technical colleges, and non-profit organizations
The team is spread across the United States and includes industry leaders in materials, equipment, small chip design, electronic design automation, and manufacturing. ASU will establish an interconnected foundry that links advanced packaging and workforce development programs with semiconductor factories and manufacturers.
Packaging Results Transformation
Scaling new semiconductor technologies from research to full production remains a significant challenge facing the industry. Major obstacles include the lack of 300mm semiconductor wafer prototype manufacturing capability facilities, as well as the lack of shared access to specialized facilities, shared infrastructure, technical resources, and capital.
Therefore, in addition to basic research, another major focus of the grants is the construction of advanced packaging capabilities. The U.S. Department of Commerce has provided Natcast with $1.1 billion in direct funding for its advanced packaging facility located in Tempe, Arizona, to operate the CHIPS for America NSTC prototype and NAPMP advanced packaging pilot facility (PPF). Natcast is a non-profit entity established specifically to operate the National Semiconductor Technology Center (NSTC) set up by the U.S. government under the CHIPS and Science Act.
Previously, the CHIPS R&amp;D facility model was announced on July 12, 2024, which includes the NSTC prototype design and the national advanced packaging manufacturing program's advanced packaging pilot facility (PPF) (expected to be operational in 2028), NSTC administrative and design facilities (expected to be operational in 2025), and the NSTC extreme ultraviolet (EUV) center (operational in 2026). These facilities will address critical gaps in the current ecosystem and provide unparalleled value to various stakeholders in the semiconductor value chain, including universities, small businesses, large manufacturers, and government agencies.
Among them, the site selection plan for the PPF was also confirmed on January 6, 2025, which will be located at the Arizona State University (ASU) research park in Tempe, Arizona. The prototype manufacturing capabilities of the PPF will include at least one 300mm full-process complementary metal-oxide-semiconductor (CMOS) technology as a stable baseline for experimentation.
According to the official website of Arizona State University, ASU is collaborating with Deca Technologies on a new project—the Advanced Wafer-Level Packaging Applications and Development Center—located at the MacroTechnology Works facility in the ASU Tempe research park. MacroTechnology Works is a semiconductor manufacturing plant acquired by Arizona State University from Motorola in 2004. The facility spans over 250,000 square feet, with more than 40,000 square feet designated as &#34;clean room&#34; space.
This is the first packaging facility in the United States with an open innovation platform, and it will become the preferred destination for researchers from industry, academia, startups, and the broader semiconductor ecosystem to gather, explore, experiment, and collaboratively develop next-generation semiconductor and packaging technologies
This move indicates that the U.S. government is not only promoting the research and development of packaging technology but also focusing on quickly applying research results to production, facilitating the rapid commercialization and scaling of innovative outcomes. These direct chip subsidies will help establish a self-sufficient, large-scale, domestic advanced packaging industry, with advanced node chips manufactured and packaged in the United States.
$3 billion, U.S. investment in six advanced packaging areas
$1.4 billion is the first step for the U.S. to strengthen advanced packaging implementation. As early as November 2023, the U.S. CHIPS National Advanced Packaging Manufacturing Program (NAPMP) will invest approximately $3 billion to develop key and related innovations in advanced packaging technology.
The CHIPS NAPMP has identified six priority research investment areas, covering all key aspects of advanced packaging, from materials and substrates to equipment and tools, as well as chip integration and multi-chip collaborative design, as shown in the figure below:
<img src="https://imageproxy.pbkrs.com/http://img.zhitongcaijing.com/images/contentformat/89c40b245897b80ef187b7ec44e6e8a2.jpg?x-oss-process=image/auto-orient,1/interlace,1/resize,w_1440,h_1440/quality,q_95/format,jpg" alt="" original-src="https://imageproxy.pbkrs.com/http://img.zhitongcaijing.com/images/contentformat/89c40b245897b80ef187b7ec44e6e8a2.jpg"/>
Packaging technology is complex and interdisciplinary, requiring interaction between various fields (Source: NIST)
Materials and substrates: Materials and substrates are the foundational platforms for advanced packaging technology. Key requirements for new substrates include multilayer fine wiring, narrow via spacing, low warpage, large area, and the ability to integrate active and passive components. These substrates can be based on silicon, glass, or organic materials and may include fan-out wafer-level processes.
Advancements in equipment, tools, and processes: Progress is needed in equipment and processes to reliably assemble chips on these substrates. CMOS devices and processes will adapt to handle chips and wafers compatible with different types of substrates.
Power transmission and thermal management: Advanced packaging has high requirements for power density and heat dissipation. To achieve success in advanced packaging, issues related to power transmission and efficient thermal management must be addressed. This requires innovative materials and solutions that must be compatible with substrates and assembly processes. These activities will involve new thermal materials and new circuit topologies using advanced substrates and heterogeneous integration.
Photonics and external connectors: Low error rate photonics and high-density, high-speed, low-loss active connectors will be essential for managing long-distance communication, necessitating new and compact solutions. The focus will be on reliable and manufacturable integrated connectors that will include computing capabilities, data preprocessing, security, and features that facilitate installation onto the package.
Developing a chiplet ecosystem: Chiplets refer to small, partially functional semiconductor chips that can form a high-functionality subsystem when assembled closely together. Methods for discovering chip fragments will be developed to ensure these chip fragments have high reusability, design capabilities, and storage capabilities.
Collaborative design and automation tools for multi-chip subsystems: These tools will adapt to the needs of advanced packaging, considering built-in testing and repair, security, interoperability, and reliability, while providing detailed insights into the substrates and processes used for assembly, including thermal and power management solutions
For the United States, a core issue of advanced packaging is the localization of the supply chain, while currently, most of the global packaging capacity is concentrated in Asia. To further consolidate the U.S. technological advantage in the field of advanced packaging, the CHIPS NAPMP will promote the construction of a domestic advanced packaging ecosystem through the following means:
Establish advanced packaging pilot facilities (or multiple facilities) to accelerate the transformation of innovations in packaging, equipment, and process development into manufacturing;
Promote the development of digital tools to reduce the time and cost of advanced packaging engineering;
Establish and support partnerships between industry, academia, training entities, and government to contribute to the advanced packaging workforce.
Conclusion
The CHIPS National Advanced Packaging Manufacturing Program and its funding support represent the strategic intent of the U.S. to achieve autonomy and control in the semiconductor supply chain. The goal for the U.S. in packaging is to establish a vibrant, self-sufficient, and profitable high-yield packaging industry by 2028, with advanced node chips being packaged in the U.S.
However, this process also faces numerous challenges, including technological complexity, global competition, and supply chain integration issues. So, can the U.S. achieve this? Let's wait and see

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The United States is accelerating the advancement of advanced packaging technology, with the Department of Commerce announcing $1.4 billion in incentive funding to enhance its leadership in this field. The investment is seen as key to the success of the semiconductor industry, particularly in improving chip performance and reducing costs. The funds will be allocated to SK subsidiary Absolics, Applied Materials, and Arizona State University, focusing on advanced substrates and materials research to address the current bottlenecks in packaging technology

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