&#34;Without TSMC, there would be no NVIDIA&#34;! Jensen Huang went to the door to &#34;request goods&#34;, and TSMC is reported to be considering expanding its capacity.
On November 14th, according to news from Chasing Wind Trading Platform, Morgan Stanley's latest research report indicates that TSMC may plan to add an additional 20,000 wafers per month of 3nm wafer capacity beyond the current expectations. The firm initially estimated TSMC's 3nm capacity in 2026 to be around 140,000 to 150,000 wafers per month, but the latest information suggests that this figure may be raised to 160,000 to 170,000 wafers per month.
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This move closely follows NVIDIA CEO Jensen Huang's recent high-profile visit to the company. During the visit, Huang publicly stated that NVIDIA's business is &#34;very strong&#34; and has requested TSMC to provide more chip supplies.
If this expansion plan is implemented, it will have a direct impact on TSMC's capital expenditures. It is estimated that the additional capacity will require approximately $5 billion to $7 billion in extra capital expenditures, potentially raising TSMC's total capital expenditures for 2026 from the current expectation of about $43 billion to a range of $48 billion to $50 billion. This potential increase in spending is seen by the market as a positive catalyst for the global semiconductor equipment industry.
This move not only reflects the continued strong demand for AI but also further confirms that the main contradiction in the current AI supply chain has shifted from backend packaging to frontend manufacturing. The report clearly states that CoWoS advanced packaging is no longer the biggest constraint, and the real shortage lies in TSMC's frontend wafer capacity and key materials such as ABF substrates.
<h2>3nm capacity is in urgent demand, TSMC may shift old production lines for expansion</h2>
As customers like NVIDIA, AMD, and Alchip rush to place orders, TSMC's 3nm capacity is becoming increasingly tight. The report points out that the industry previously believed that TSMC wanted to maintain full utilization of its advanced process capacity, thus taking a cautious approach to expansion. However, after major AI customers like NVIDIA made requests, its 3nm capacity plans may have changed.
According to TSMC management's statements during the earnings call, all newly built cleanroom space in Taiwan will be used for the expansion of 2nm processes. This means that the expansion of 3nm will need to take place within existing wafer fabs. To address the space issue, Morgan Stanley's latest survey indicates that TSMC may consider moving its 22/28nm equipment from the Fab15 wafer fab and reserving this equipment for future use in European factories, thereby freeing up valuable cleanroom space for the new 3nm production line.
According to the firm's predictive model, this adjustment will raise TSMC's total 3nm capacity in 2026 from the previously estimated 140,000 to 150,000 wafers per month to 160,000 to 170,000 wafers per month.
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<h2>Capital expenditures may be significantly increased, benefiting equipment manufacturers</h2>
Behind capacity expansion is a massive capital investment. Analyst Charlie Chan estimated in a report that with a capital expenditure of $300 million required for every 1,000 3-nanometer wafers, an additional capacity of 20,000 wafers per month would correspond to an investment of $5 billion to $7 billion, potentially pushing TSMC's total capital expenditure for 2026 to a range of $48 billion to $50 billion.
This additional expenditure will significantly raise TSMC's capital expenditure forecast for 2026. The report believes that this potential increase in capital expenditure is positive for the global semiconductor equipment industry sentiment. The firm also reaffirmed its &#34;overweight&#34; rating on industry companies such as TSMC, King Yuan Electronics, and ASE Technology.
Changes in TSMC's capital expenditures are a key barometer for observing the semiconductor industry's prosperity. An increase in capital expenditure typically indicates that the company has strong confidence in future market demand, which will directly benefit upstream equipment suppliers.
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<h2>CoWoS is no longer a bottleneck, front-end wafers become key</h2>
For some time, the market has generally viewed CoWoS advanced packaging technology as the main bottleneck for AI chip supply. However, the report emphasizes that this view may be outdated.
The report analyzes that although major tech companies have announced large-scale data center power deployment plans, when translating this into demand for CoWoS, calculations show that TSMC and other manufacturers' CoWoS capacity should be sufficient to meet the demand. The report points out that the real bottleneck lies in front-end wafer manufacturing capacity, as well as the supply of other materials such as ABF substrates and T-Glass (glass substrates).
This judgment has also been indirectly confirmed by the industry chain. According to a Reuters report, ASIC design service company Alchip has reiterated the dilemma of 3-nanometer wafer shortages. This indicates that even if back-end packaging capacity is sufficient, if front-end wafer supply is inadequate, the final output of AI chips will still be limited.
<h2>AI demand remains strong, customers like NVIDIA scramble for capacity</h2>
The fundamental driving force behind TSMC's consideration of urgent capacity expansion stems from the insatiable &#34;computing power hunger&#34; of AI giants led by NVIDIA. Jensen Huang candidly stated during his visit to Taiwan, &#34;Without TSMC, there would be no NVIDIA today,&#34; clearly revealing the deep dependence of its growth on TSMC's capacity.
According to the report, in the composition of customer demand for TSMC's 3-nanometer process, NVIDIA and another U.S. customer are the largest sources of demand, and it is expected that they will dominate from 2025 onwards. Additionally, the report predicts that by 2025, AI-related revenue will account for 25% of TSMC's total revenue.
From Tesla's 3-nanometer AI5 chip design to major cloud service providers' ongoing investments in AI servers, all signs point to one conclusion: demand for the most advanced process chips will continue to grow strongly in the foreseeable future. TSMC's consideration of capacity expansion is a direct response to this market trend and indicates that the global semiconductor industry's capital competition will continue
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SOXL

Morgan Stanley expects that in response to strong demand from major AI customers such as NVIDIA, Taiwan Semiconductor is considering increasing its 3-nanometer capacity target for 2026 by an additional 20,000 wafers per month on top of the original plan, bringing total capacity to 160,000-170,000 wafers per month. This move could significantly boost its capital expenditure for 2026 to $48-50 billion, far exceeding market expectations. This is also seen by the market as a positive catalyst for the global semiconductor equipment industry

- TSMC is reportedly considering increasing its 3-nanometer wafer capacity by an additional 20,000 wafers per month, raising its total capacity forecast for 2026 from 140,000-150,000 to 160,000-170,000 wafers per month.  
- This potential expansion follows NVIDIA CEO Jensen Huang's recent visit, where he emphasized the strong demand for chips, prompting TSMC to reassess its production plans.  
- If implemented, the expansion could increase TSMC's capital expenditures significantly, from an expected $43 billion to a range of $48 billion to $50 billion, positively impacting the semiconductor equipment industry.

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Taiwan Semiconductor

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After Jensen Huang's visit to Taiwan and his request for "production capacity," is Taiwan Semiconductor urgently adding expansion plans? It may raise capital expenditures for 2026