Morgan Stanley's latest research report cuts through the noise of AI infrastructure investment, and based on on-site research of the Asian supply chain, answers the five core questions of greatest market concern: NVIDIA's Rubin Ultra packaging solution, LPU foundry selection, Samsung's HBM base die transition to TSMC, the impact of Broadcom and Google's cooperation on MediaTek, and the actual meaning of new computing power deployment for chip demand.
In the field of advanced packaging, Morgan Stanley stated that TSMC's monopolistic position in CoWoS/SoIC continues to strengthen, with capacity expected to expand to 160,000-170,000 wafers per month by 2027, sufficient to meet the surging demand for computing power. However, ultra-large chip designs still face technical challenges such as interposer warpage.
In terms of custom chips, MediaTek's 3nm TPU (ZebraFish) developed for Google is progressing smoothly and is expected to enter mass production in the second half of 2026. The report maintains revenue forecasts of $1.6 billion for 2026 and $10 billion for 2027, considering them decisive for MediaTek's valuation re-rating.
In terms of the foundry landscape, NVIDIA is gradually introducing Samsung as a supplement to TSMC. The LP35 node in 2027 may adopt a dual-supplier strategy, breaking the expectation that TSMC exclusively holds NVIDIA's advanced process manufacturing.
<h2>NVIDIA Rubin Ultra: 2 or 4 Dies per Chip Package? What are the Implications?</h2>
The market is highly focused on whether NVIDIA's 2027 Rubin Ultra will use 2 or 4 compute dies within a single package. This fundamentally depends on whether TSMC's CoWoS-L technology can support chip designs up to 9 reticle sizes in a cost-effective manner—a solution that would include 4 compute dies, 2 I/O dies, and 8 to 10 HBMs.
Regardless of whether Rubin Ultra ultimately adopts a 2-die or 4-die configuration, it will not substantially change NVIDIA's consumption of TSMC's wafer capacity. TSMC's CoWoS roadmap indicates support for 9 reticles by 2027, which is technically feasible, but reliability issues such as interposer warpage still need to be resolved. If these technical bottlenecks cannot be overcome, Intel's EMIB-T may capture market share from TSMC in projects like Google's 2nm TPU.
<h2>NVIDIA LPU Demand Surge: Who Benefits, Samsung or TSMC?</h2>
NVIDIA's Groq 3 LPU is scheduled for release in the second half of 2026, featuring liquid-cooled LPX racks. Each server cabinet will be configured with 256 LPUs, each with 128GB of on-chip SRAM and 640 TBps of extended bandwidth, focusing on low-latency AI inference scenarios. The current LP30 version is produced using Samsung's 7nm process.
Supply chain investigations indicate that starting from LP35 (4nm)—a product slated for mass production in 2027 alongside Rubin Ultra—NVIDIA may adopt a dual-supplier procurement strategy between TSMC and Samsung. LP40 (expected 3nm), planned for launch in 2028 with the Feynman platform, will utilize discrete SRAM and TSMC's SoIC 3D stacking solution.
In terms of SoIC capacity, TSMC expects to reach 14,000 wafers per month in 2026, increase to 28,000 in 2027, and further expand to 45,000 per month in 2028.
<h2>Will Korean HBM Base Die Shift to TSMC's 3nm?</h2>
As HBM4e and HBM5 require extensive custom design and IP support for their base dies, TSMC's 3nm process will become a crucial node for global HBM base die production from 2028.
Latest supply chain information indicates that TSMC will convert 10,000 to 20,000 wafers per month of 4/5nm capacity at Fab 18 Phase 3 to 3nm, preparing for the custom HBM4e and HBM5 base die demand, including from Korean HBM suppliers.
In terms of investment implications, AI memory (including SRAM and HBM base dies) will become a significant growth driver for TSMC from 2028 onwards.
<h2>How do Broadcom and Google's Announcements Affect MediaTek's TPU Opportunities?</h2>
The announcement of cooperation between Broadcom and Google initially raised market doubts about MediaTek's strategic position in the TPU supply chain. However, the report clearly states that this event does not change the positive outlook for MediaTek's 3nm TPU (ZebraFish).
Supply chain checks confirm that ZebraFish will begin mass production in the second half of 2026 as planned. The shipment assumption of 400,000 units in 2026 (corresponding to approximately $1.6 billion in revenue) &#34;should be solidly achievable.&#34; Currently, the 3nm TPU is undergoing ECO modifications for several metal layers due to slightly higher-than-expected power consumption, but this does not affect the mass production timeline. Google is concurrently conducting test validations. The mass production phase will use a new set of reticles incorporating design changes, ensuring more stable chip performance and quality.
More importantly, the report is optimistic about MediaTek's ABF substrate supply in 2027, reiterating its highest market forecast: 2.5 million units shipped in 2027, contributing approximately $10 billion in revenue, and maintaining an &#34;Outperform&#34; rating.
From the perspective of the complete Google TPU shipment forecast, the total volume is expected to grow from 2.4 million units in 2024 to 6 million units in 2027 and 7 million units in 2028. MediaTek's ZebraFish (v8, 3nm) and HumuFish (v10, 2nm) will contribute significant shares from 2026 to 2027, respectively.
<h2>How Much Chip Demand Does New Computing Power Deployment Imply?</h2>
Recently, the market has announced numerous computing power deployment plans, including the 2GW project from AWS in partnership with OpenAI and the 3.5GW project from Google in partnership with Broadcom. Translating these substantial power data into specific wafer demand, the core conclusion is: Power is not the bottleneck for TSMC's chip demand; ABF substrates and HBM supply are the real constraints.
According to estimates, over the entire lifecycle of the aforementioned projects, the implied total consumption of TSMC's CoWoS is approximately 953,000 wafers, with front-end 2nm and 3nm wafer consumption around 652,000 wafers. Assuming OpenAI-related contracts are executed within three years, these projects are expected to require an annual CoWoS demand of 259,000 wafers for TSMC by 2027.
Morgan Stanley believes this target is entirely achievable, as TSMC plans to expand its total CoWoS capacity to 160,000 to 170,000 wafers per month (160-170kwpm) by the end of 2027, which is sufficient to cover the incremental demand.

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Morgan Stanley stated that TSMC's monopolistic position in CoWoS/SoIC continues to strengthen, with capacity expected to expand to 160,000-170,000 wafers per month by 2027. MediaTek's 3nm TPU developed for Google is progressing smoothly. NVIDIA will introduce Samsung as a second supplier in 2027. AI memory will become a significant growth engine for TSMC from 2028. Power is not the bottleneck for chip demand; ABF substrates and HBM supply are the key constraints

- Morgan Stanley's latest report addresses key issues in AI infrastructure investment based on on-site research in Asian supply chains, including Nvidia's packaging options and Mediatek's forecasts.  
- The report highlights TSMC's monopoly in advanced packaging and predicts strong growth for Mediatek's custom chips, especially with the upcoming mass production of its 3nm TPU, contributing significant revenue.  
- It also notes that upcoming power deployment plans by major companies will not constrain TSMC's chip demand, as supply chain factors like ABF substrates and HBM are more critical.

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Morgan Stanley: Addressing Five Core Questions on Asia's AI Semiconductor Supply Chain