SK Hynix: General HBM, next stop is custom HBM?

Recently, storage has been bearish, following the logic of a cyclical stock script: a wave of concentrated capacity expansion landing in 2027–2028 → supply catching up with demand → prices peaking → valuation de-rating.

Storage is priced as if it were"a commodity standard part where who makes it doesn't matter" (commodities, cyclical stocks), but the underlying physical technology is also evolving. In the hardware world, one type of product only needs to ensure stable, routine operation; while another type carries a geek spirit, exceeding standard parameters to achieve more extreme performance and efficiency.

In the CPU era, Intel handled routine workflow scenarios, while AMD, building on this, always exceeded certain performance levels (in gaming).

In the GPU era, NVIDIA secured the entry point for training models with general-purpose GPUs, while AMD and ASIC customizations represented by Broadcom and Marvell went ahead to compete for the share needed for AI inference (performance GPUs).

HBM is also undergoing a three-step evolution:

1. Process Switch (HBM4)

The base chip (base die) switches from DRAM process to logic process. The interface bandwidth doubles with each generation of HBM (from 1024bit in HBM3 to 2048bit in HBM4), and all data must pass through this base die.

• SK Hynix uses TSMC's 12nm process, while Samsung uses its own 4nm foundry for 代工 (foundry services).
• Due to cost considerations, Micron keeps HBM4 in the DRAM process, switching to TSMC's logic process only for HBM4E, but the design still belongs to the storage manufacturers at this stage.

2. cHBM (Custom HBM) — Moving the circuits responsible for communication between the GPU and storage (memory controller, interface) down into the base die. This frees up valuable area on the GPU for compute power, allows for on-site preprocessing/compression, reduces data movement, and saves power.

There are several design approaches: storage manufacturers build according to customer specifications, partners like Marvell jointly define them with the top three storage makers, or customers design them themselves (NVIDIA's self-developed approach).

Once the customer-defined logic circuits enter the base die, this HBM becomes a customer-exclusive component, not sold to others, and the customer cannot switch suppliers.

3. memory-on-logic

By the time we reach cHBM, the base die already resembles the customer's logic chip. So, why not have a separate base die? Instead, place the compute die directly in that position, with 3D-stacked storage on top. Connection density jumps from tens of thousands of points to hundreds of thousands, and signal distance shrinks from millimeter-level wiring to tens of micrometers vertically. Latency is lower, and data interaction throughput is higher.

A 2025 paper by Georgia Tech + SK Hynix estimates: throughput is 64 times that of 2.5D, and energy efficiency is 3 times higher (academic modeling, only indicating direction and magnitude). The unsolved problem is heat dissipation: DRAM stacked on a compute die generating hundreds of watts blocks heat dissipation paths and absorbs heat itself. At high temperatures, spacing shortens and performance degrades. How to solve heat dissipation is the biggest variable for the success or failure of memory-on-logic.

In the coming years, cHBM is the most realistic commercialization path, while memory-on-logic is more radical and requires solving heat dissipation and yield issues first. The technological evolution of both may run in parallel for a period for verification.

Industry progress is moving.

• cHBM is already on the roadmap: Rumors suggest NVIDIA's Feynman generation in 2028 will use cHBM (not officially confirmed); Samsung, Hynix, and Micron have all included cHBM in their official R&D roadmaps; $Marvell Tech(MRVL.US) has announced joint development with the top three manufacturers.

• There are already implementation cases for memory-on-logic: Qualcomm announced HBC at its June 2026 Investor Day, with its AI250 accelerator planned for mass production in mid-2027. HBC uses LPDDR (not HBM), with a dedicated near-memory accelerator underneath (not the GPU itself), effectively bypassing two bottlenecks: HBM shortages and advanced packaging shortages.

Using low-power accelerators + low-power LPDDR to suppress heat dissipation issues. Qualcomm claims that per-watt bandwidth is 6 times that of HBM, and per-watt capacity is 200 times that of on-chip SRAM (pending real-machine verification).

Who are the ordering customers? Saudi Arabia's Humain has included the AI250 rack in its deployment plan. Reports indicate that Microsoft's Nadella also mentioned deploying Qualcomm HBC on Azure.

Other dynamics: Since 2023, SK Hynix has been discussing direct stacking of HBM onto processors with fabless companies like NVIDIA. Taiwanese ASIC design firm GUC proposed DoL (DRAM-on-Logic).

Bulls are still looking for the inflection point for business model revaluation: The closer storage business gets to custom silicon, the easier it is to break free from the category attributes of commodities (hard currency).

If the top three storage manufacturers revert to the cyclical stock logic, they will inevitably focus on bit growth and ASP pricing. However, the revenue structure and gross margin changes brought by customization have not yet entered financial report figures, nor any valuation models — this might be exactly the upside space that the market hasn't priced in yet.

[Prize Discussion]

What do you think about Hynix's future performance in light of this? What are your impressions of this earnings report? Share your views on the AI storage cycle!

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