I'm LongbridgeAI, I can summarize articles.Alibaba Damo Academy released the new generation RISC-V CPU Xuantie C950 in Shanghai. This processor achieved a single-core performance score of over 70 in the SPECint2006 benchmark test, setting a new global record. It has a clock frequency of 3.2GHz, supports RVA23.1 extensions, and integrates secure computing capabilities. The Xuantie C950 also innovatively integrates AI dual engines, including Vector and Matrix acceleration engines, supporting up to 8T FLOPS computing power. Damo Academy has reached strategic cooperation with multiple parties to jointly develop the next generation of high-performance RISC-V CPUs, promoting the industrialization of the RISC-V ecosystem
PingWest reported on March 25th that Alibaba's Damo Academy recently held the XuanTie RISC-V Ecosystem Conference in Shanghai. At the conference, Damo Academy officially launched the new generation flagship RISC-V CPU, XuanTie C950, which achieved a single-core general performance score of over 70 in the SPECint2006 benchmark test, setting a new global performance record for RISC-V processors.
The CPU has a clock speed of up to 3.2GHz, supports the complete RVA23.1 extension, and integrates CoVE native security computing capabilities. To embrace the AI wave, the XuanTie C950 innovatively integrates the RISC-V native "AI Dual Engines"—the Vector Acceleration Engine and the Matrix Acceleration Engine. The Vector Engine supports a maximum bit width of 4096-Bit, while the Matrix Engine can provide up to 8T FLOPS (FP8) computing power per core, aiming to combine high-performance general computing power with AI computing power. This chip has achieved native support for large models with hundreds of billions of parameters, such as Qwen3 and DeepSeek V3.
Currently, the XuanTie series CPUs have been widely deployed in cloud computing, high-end robotics, AI terminals, and other fields, empowering over 200 chip mass productions. At the conference, Damo Academy also reached a strategic cooperation with the Beijing Open Source Chip Research Institute and the Institute of Software, Chinese Academy of Sciences, to jointly develop the next generation high-performance RISC-V CPU "Xiangshan," working together to promote the industrialization process of the RISC-V ecosystem.
