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Advanced Semiconductor Engineering

ASX

37.9502.24% ( +0.830 )
Closed: Sep 16, 16:00:00 (EDT)
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  • A
    AI GossipSep 7 at 07:56 AM

    Below is a summary from an article by Calvin Lee, Director of Corporate R&D of ASE who is leading 3D IC packaging development.

    For investors, the key point is that microbumps have a surprisingly long runway as packaging complexity increases. Their ability to scale within existing backend manufacturing flows makes them a lower-risk path for expanding advanced packaging capacity, while hybrid bonding remains concentrated in applications where its incremental performance justifies the substantially higher manufacturing requirements....

    'Microbumps and Hybrid Bonding both enable high-density die-to-die and die-to-wafer integration, but they impose very different requirements on the manufacturing process. Those differences are important because they help explain why microbumps remain the preferred solution for high-volume production today.

    👉Manufacturing maturity:

    Microbump processing builds on manufacturing infrastructure that OSATs and foundries already have in place: electroplating, resist patterning, UBM formation and reflow. The key challenge is continuing to push toward finer pitches, with 40–100µm already established and 20µm becoming an important target. This is largely an extension of existing processes rather than a fundamental change in the manufacturing environment.

    Hybrid bonding requires a much tighter process flow. Surface preparation, CMP, plasma activation, contamination control and sub-micron alignment all become critical. In practice, this introduces more frontend-like process requirements into the packaging flow, increasing both capital intensity and process complexity. That makes hybrid bonding considerably more difficult to deploy across a broad manufacturing base.

    👉Supply chain and process control:

    The microbump ecosystem is mature. Copper, nickel, solder alloys, UBM materials and the associated equipment are available from a broad supplier base, and the process is sufficiently tolerant to support multisourcing and production across different facilities.

    Hybrid bonding is more sensitive to relatively small variations in surface roughness, wafer flatness, oxide properties, contamination and bonding conditions. As a result, process recipes and equipment become more tightly coupled, making qualification, second sourcing and transferring production between sites more difficult. For an investor, this matters because it can translate into longer qualification cycles, higher switching costs and greater execution risk during capacity expansion.

    👉Alignment and yield:

    Microbumps also have a fundamental advantage in process tolerance. The solder-based connection provides some mechanical compliance during assembly and reflow, helping absorb modest alignment errors, wafer bow and thermal mismatch. That becomes increasingly valuable as package dimensions increase and heterogeneous dies are combined.

    Hybrid bonding removes much of that tolerance in exchange for substantially higher interconnect density. Direct copper-to-copper or oxide-to-oxide bonding requires extremely tight control of alignment and surface condition. Defects that would be tolerated in a conventional microbump flow can instead become yield limiters. The result is a narrower process window and a more demanding yield-learning curve, particularly as die sizes and stack heights increase.

    👉The OSAT perspective:

    This is where the distinction becomes particularly important. Microbumps already provide the density, bandwidth and power characteristics required for chiplets, HBM and large 2.5D packages, while remaining compatible with established backend processes such as RDL formation, known-good-die assembly and chip-on-wafer bonding.

    The technology is also continuing to scale. VIPack, for example, is targeting a progression from roughly 40µm toward 20µm pitch through improvements in the metallurgical stack rather than a wholesale change in the packaging architecture.

    Hybrid bonding will increasingly matter where interconnect density and electrical performance justify the additional process complexity, particularly for demanding 3D logic and future memory architectures. But for much of the market, microbumps offer a compelling trade-off: sufficient interconnect density, a mature equipment and materials ecosystem, broader manufacturing flexibility and a more forgiving yield profile.'

    Source: Chips & Wafers

  • A
    AI GossipAug 30 at 10:56 PM

    Strong demand for Google Tensor Processing Units (TPUs), Intel outsourcing more as it focuses on EMIB, and price increases due to rising costs and demand are all converging into a boom of advanced packaging and testing orders for ASE Technology, media report, adding Google has aggressively expanded TPU volume via partners including Broadcom, MediaTek, Marvell and AMD, leading to substantial add-on orders at ASE. Estimates put Google TPU shipments at 12 to 15 million units by 2028. TSMC remains Google’s chip fabrication and CoWoS partner, with ASE also a major winner from the TPU ramp up. $Advanced Semiconductor Engineering(ASX.US) $Alphabet(GOOGL.US) $Intel(INTC.US) #semiconductors

    Source: Dan Nystedt

    Advanced Semiconductor Engineering

    Advanced Semiconductor Engineering

    USASX

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    AI GossipAug 21 at 01:56 AM

    Taiwan’s July export orders rose 61.9% year-on-year to a fresh record high US$97.94 billion and beating the expected 52.7% increase, media report. The US led all others with orders up 88.9% to $40.79B, the fastest pace of growth ever. Orders for IT/communications products, including servers & networking gear, rose 89.5% to $33.27B on strong AI and cloud service demand, while Electronics Products, including semiconductors and chip manufacturing services, rose 71.7% to $41.32 billion. In August, officials see export orders nearing $100B, up 61.4% - 64.8%. $Taiwan Semiconductor(TSM.US) $United Microelectronics(UMC.US) $Advanced Semiconductor Engineering(ASX.US) #Foxconn #Quanta #Wistron

    Source: Dan Nystedt

    Advanced Semiconductor Engineering

    Advanced Semiconductor Engineering

    USASX

  • A
    AI GossipAug 19 at 02:46 AM

    Rumor: Intel Malaysia took over some advanced packaging for TSMC due to a surge in orders for CoWoS packaging by a major mutual client, media report, adding ASE, Unimicron, Gudeng Precision and others are also expected to benefit from the move. TSMC is expected to ship more advanced chips as the packaging bottleneck eases. $Intel(INTC.US) $Taiwan Semiconductor(TSM.US) $Advanced Semiconductor Engineering(ASX.US) $Alphabet(GOOGL.US) $NVIDIA(NVDA.US) #semiconductors

    Source: Dan Nystedt

    Advanced Semiconductor Engineering

    Advanced Semiconductor Engineering

    USASX

  • A
    AI GossipAug 18 at 12:26 AM

    When Nvidia announced Spectrum-X switches built with CPO (co-packaged optics) have entered mass production, it named 4 Taiwan firms among partners, TSMC, Foxconn, ASE and Browave as well as China’s leading optics firm, TFC Communication, media report, and multiple firms say their order books are already full through 2027 and expect supplies to be tight into 2028.

    CoreWeave, Lambda and Oracle will become the first to deploy the 200Gbps/lane CPO Ethernet switch system, billed for a big leap in performance:

    5x improvement in network power efficiency

    5x increase in continuous AI uptime

    10x extension in Mean Time Between Failures (MTBF)

    Up to 1.6x overall AI network performance boost, supports 100s of 1000s of GPUs

    TSMC and Foxconn are expected to play key roles, with TSMC leading production via its COUPE silicon photonics engine platform, which integrates components that are then packaged by ASE and use Browave’s optical components. Foxconn does final assembly of the CPO switches.

    Foxconn Chairman Young Liu has said CPO switch shipment volumes will reach 10,000 units this year, with 2027 shipments multiplying several times over.

    Taiwan’s FOCI and ShunSin have secured key niches in the supply chain, with FOCI’s expertise in Fiber Array Units (FAU) and ShunSin’s advanced packaging mass production prowess, media say, calling them key winners further down the supply chain. $NVIDIA(NVDA.US) $Taiwan Semiconductor(TSM.US) $Advanced Semiconductor Engineering(ASX.US) $Oracle(ORCL.US) $Coreweave(CRWV.US)

    Source: Dan Nystedt

    Advanced Semiconductor Engineering

    Advanced Semiconductor Engineering

    USASX

  • A
    AI GossipAug 12 at 12:46 AM

    Siliconware Precision (SPIL) broke ground Tuesday on an NT$100 billion (US$3.1B) CoWoS advanced packaging plant in Douliu, central Taiwan, aimed at massive AI-related demand, media report, adding SPIL’s new plant investments in the past 2-years total NT$200 billion. SPIL is a key Nvidia packaging partner. TSMC outsources some parts of CoWoS work to the group SPIL is part of, ASE Holding. TSMC will also certify ‘copy exact’ partners, which SPIL’s facilities are designed to match. $Advanced Semiconductor Engineering(ASX.US) $Taiwan Semiconductor(TSM.US) $NVIDIA(NVDA.US) #semiconductors

    Source: Dan Nystedt

    Advanced Semiconductor Engineering

    Advanced Semiconductor Engineering

    USASX

  • A
    AI GossipAug 10 at 07:59 AM

    🚨 $Advanced Semiconductor Engineering(ASX.US) JULY '26 ATM REVENUE🚨

    $1.48B, Fresh ATH

    +36% YoY

    +35% YTD

    +8% MoM

    Source: Chips & Wafers

    图片 1,共 1 张
    Advanced Semiconductor Engineering

    Advanced Semiconductor Engineering

    USASX

  • A
    AI GossipAug 6 at 06:22 PM

    $Advanced Semiconductor Engineering(ASX.US) filed ~$160M of equipment POs in the last 48hrs:

    $36M Advantest + $35M Hon Precision handlers at SPIL, filed an hour apart - full test cells.

    Advantest POs hit the disclosure threshold in 3 weeks vs 12 months for the handlers.

    Plus a $50M ASMPT batch at ASE - likely TCBs - and $39M of All Ring Tech dispensing/automation for the packaging lines.

    Source: Chips & Wafers

    图片 1,共 1 张
    Advanced Semiconductor Engineering

    Advanced Semiconductor Engineering

    USASX

  • A
    AI GossipAug 5 at 02:56 AM

    ABF substrate makers are being forced to move faster on expansion plans as AI chip die get bigger, driving demand for larger substrates, media report, noting long term agreements (LTAs) are no longer enough: clients are paying firms to launch 2029-2030 expansion plans now, using a variety of methods:

    -prepayments

    -client pays for production line equipment

    -joint factory construction and more

    -Unimicron raised 2026 capex to NT$53.7 billion

    -ZDT Group subsidiary, Leading Interconnect (China) to expand to 7 or more plants in Shenzhen by 2030

    -Kinsus Interconnect added NT$19.6 billion in capex over 3-years (projected NT$14B 2026 and NT$16B 2027)

    -Nan Ya PCB is seen raising capex to expand existing plants, and will lease & convert a plant in south Taiwan

    AMD CEO Lisa Su recently visited Taiwan, announcing US$10 billion in investments aimed at the supply chain, including the EFT (Elevated Fanout Bridge) advanced packaging ecosystem – and media say substrate makers figure prominently in that. $AMD(AMD.US) $NVIDIA(NVDA.US) $Taiwan Semiconductor(TSM.US) $Advanced Semiconductor Engineering(ASX.US) $Amkor Tech(AMKR.US) #Unimicron #Kinsus #NanYaPCB

    Source: Dan Nystedt

    Advanced Semiconductor Engineering

    Advanced Semiconductor Engineering

    USASX

  • A
    AI GossipJul 31 at 02:26 AM

    AUO, the display panel maker, plans to spend NT$8.64 billion (US$267M) for an FOPLP advanced chip packaging pilot line that uses glass substrates: Glass Core (structure), Redistribution Layer (RDL, fine metal wiring) and Through Glass Via (TGV, tiny holes drilled through the glass to connect layers). FOPLP plans aim at LEO satellite antennas, Micro LEDs and optical communications. AUO’s main rival in Taiwan, Innolux, has already started developing its advanced semiconductor packaging business. In February, AUO’s board approved NT$14.67B in capex spending. $Taiwan Semiconductor(TSM.US) $Advanced Semiconductor Engineering(ASX.US) $Amkor Tech(AMKR.US) #advancedpackaging #semiconductors

    Source: Dan Nystedt

    Advanced Semiconductor Engineering

    Advanced Semiconductor Engineering

    USASX